OPERATIONAL MODES RESET SOURCE High Temper" />
參數(shù)資料
型號： MM908E621ACDWB
廠商： Freescale Semiconductor
文件頁數(shù)： 22/60頁
文件大?。?/td> 0K
描述： IC QUAD HALF BRDG TRPL SW 54SOIC
標準包裝： 26
應用： 自動鏡像控制
核心處理器： HC08
程序存儲器類型： 閃存（16 kB）
控制器系列： 908E
RAM 容量： 512 x 8
接口： SCI，SPI
輸入/輸出數(shù)： 12
電源電壓： 9 V ~ 16 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 54-BSSOP（0.295"，7.50mm 寬）裸露焊盤
包裝： 管件
供應商設備封裝： 54-SOICW-EP
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
908E621
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
RESET SOURCE
High Temperature Reset
The device is protected against high temperature. When
the chip temperature exceeds a certain temperature, a reset
(HTR) is generated. The reset is flagged by the HTR bit in the
Interrupt Flag Register. A HTR event will reset all registers in
the SPI excluding the RSR.
The HTR can be disabled by bit HTRD in the Interrupt
Mask register.
Note: Disabling the high temperature reset can lead to
destruction of the part in cases of high temperature. This bit
was foreseen for test purposes only!
Watchdog Reset
The watchdog module generates a reset, because of a
watchdog timeout or wrong watchdog timer reset. Reset is
flagged by the WDR bit in the Reset Status Register. A
watchdog reset event will reset all registers in the SPI
excluding the RSR.
Main VREG Low Voltage Reset
The LVR is related to the Main VDD. If the voltage falls
below a certain threshold, it will pull down the RST_A pin.
Reset is flagged by the LVR bit in the Reset Status Register.
An LVR event will reset all register in the SPI excluding the
RSR.
Power On Reset
The POR is related to the internal 5.0 V supply. If the
device detects a power on, the POR bit in the Reset Status
Register (RSR) is set. A power on reset will reset all register
in the SPI including the RSR and set the POR bit.
The Power On Reset circuitry will force the RST_A pin low
for tRST after the VDD has reached its nominal value (above
LVR Threshold). Also see Figure 10, page 18).
Reset Pin / External Reset
An external reset can be applied by pulling down the
RST_A pin. The reset event is flagged by the PINR bit in the
reset status register.
Reset Status Register
This register contains five flags that shows the source of
the last reset. A power-on-reset sets the POR bit and clears
all other bits in the Reset Status Register. All bits can be
cleared by writing a one to the corresponding bit. Uncleared
bits remain set as long as they are not cleared by a power-
on-reset or by software.
In addition, the register includes two flags which will
indicate the source of a wake-up from Sleep mode: Either LIN
bus activity, or an event on the L0 wake-up input pin.
POR— Power On Reset bit
This read/write bit is set after power on. Bit is cleared by
writing a logic “1” to this location.
1 = Reset due to power on
0 = no power on reset
PINR— Reset Forced from External Reset Pin Bit
This read/write bit is set after a reset was forced on the
external reset RST_A pin. The bit is cleared by writing an
logic “1” to this location.
1 = reset source is external reset pin
0 = no external reset
WDR— Watch Dog Reset Bit
This read/write flag is set due to a watchdog timeout or
wrong watchdog timer reset. Clear WDR by writing a logic “1”
to WDR.
1 = reset source is watchdog
0 = no watchdog reset
HTR— High Temperature Reset Bit
This read/write bit is set if the chip temperature exceeds a
certain value. The bit is cleared by writing a logic “1” to this
location.
1 = reset due to high temperature condition
0 = no high temperature reset
LVR— Low Voltage Reset Bit
This read/write bit is set if the external VDD voltage coming
from the main voltage regulator falls below a certain value.
The bit is cleared by writing a logic “1” to this location.
1 = reset due to low voltage condition
0 = no low voltage reset
LINWF— LIN Wake-up Flag
This read/write bit is set if a bus activity was the case of an
wake-up. The bit is cleared by writing a logic “1” to this
location.
1 = Wake-up due to bus activity
0 = no wake-up due to bus activity
L0WF— L0 Wake-up Flag
This read/write bit is set if a event on the L0 pin caused an
wake-up. The bit is cleared by writing a logic “1” to this
location.
Register Name and Address: RSR - $0D
Bit7
6
5
4
3
2
1
Bit0
Read
POR
PINR
WDR
HTR
LVR
0
LINWF LOWF
Write
POR
1
0
相關PDF資料
PDF描述
MM908E624ACDWB IC TRPL SWITCH MCU/LIN 54-SOIC
MM908E624ACDWBR2 IC TRPL SWITCH MCU/LIN 54-SOIC
046232108015800+ CONN FFC/FPC 8POS 1MM VERT SMD
SST26VF032A-80-5I-QAE IC FLASH 32MBIT 8WSON
07FMN-BMTR-A-TB CONN FMN HOUSNG 7POS SGL REV SMD
相關代理商/技術參數(shù)
參數(shù)描述
MM908E621ACDWB/R2 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Quad Half-bridge and Triple High Side with Embedded MCU and LIN for High End Mirror
MM908E621ACDWBR2 功能描述:8位微控制器 -MCU QUAD HB / TRIPLE HS 841B RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
MM908E621ACPEK 功能描述:8位微控制器 -MCU QUAD H-B/3-HS W/MCU & LI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
MM908E621ACPEKR2 功能描述:8位微控制器 -MCU QUAD HB AND TRIPLE HS RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
MM908E622 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Quad Half-Bridge, Triple High-Side and EC Glass Driver with Embedded MCU and LIN for High End Mirror
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*