DYNAMIC ELECTRICAL CHARACTERISTICS DYNAM" />
參數(shù)資料
型號: MM908E621ACDWB
廠商: Freescale Semiconductor
文件頁數(shù): 6/60頁
文件大?。?/td> 0K
描述: IC QUAD HALF BRDG TRPL SW 54SOIC
標(biāo)準(zhǔn)包裝: 26
應(yīng)用: 自動鏡像控制
核心處理器: HC08
程序存儲器類型: 閃存(16 kB)
控制器系列: 908E
RAM 容量: 512 x 8
接口: SCI,SPI
輸入/輸出數(shù): 12
電源電壓: 9 V ~ 16 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 54-BSSOP(0.295",7.50mm 寬)裸露焊盤
包裝: 管件
供應(yīng)商設(shè)備封裝: 54-SOICW-EP
Analog Integrated Circuit Device Data
14
Freescale Semiconductor
908E621
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the
microcontroller chip. Characteristics noted under conditions 9.0V VSUP 16V, -40°C TJ 125°C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LIN PHYSICAL LAYER
Driver Characteristics for Normal Slew Rate(28), (29)
Dominant Propagation Delay TXD to LIN
tDOM-MIN
——
50
μs
Dominant Propagation Delay TXD to LIN
tDOM-MAX
——
50
μs
Recessive Propagation Delay TXD to LIN
tREC-MIN
——
50
μs
Recessive Propagation Delay TXD to LIN
tREC-MAX
——
50
μs
Duty Cycle 1: D1 = tBUS_REC(MIN) / (2 x tBIT), tBIT = 50 μs, VSUP = 7.0V…18V
D1
0.396
Duty Cycle 2: D2 = tBUS_REC(MAX) / (2 x tBIT), tBIT = 50 μs, VSUP = 7.6 V18 V
D2
0.581
Driver Characteristics for Slow Slew Rate(28), (30)
Dominant Propagation Delay TXD to LIN
tDOM-MIN
100
μs
Dominant Propagation Delay TXD to LIN
tDOM-MAX
100
μs
Recessive Propagation Delay TXD to LIN
tREC-MIN
100
μs
Recessive Propagation Delay TXD to LIN
tREC-MAX
100
μs
Duty Cycle 3: D3 = tBUS_REC(MIN) / (2 x tBIT), tBIT = 96 μs, VSUP = 7.0V…18V
D3
0.417
Duty Cycle4: D4 = tBUS_REC(MAX) / (2 x tBIT), tBIT = 96 μs, VSUP = 7.6V…18V
D4
0.590
Driver Characteristics for Fast Slew Rate
LIN High Slew Rate (Programming Mode)
SRFAST
—20
V/
μs
Receiver Characteristics and Wake-up Timings
Receiver Dominant Propagation Delay(31)
tRL
—3.5
6.0
μs
Receiver Recessive Propagation Delay(31)
tRH
—3.5
6.0
μs
Receiver Propagation Delay Symmetry
tR-SYM
-2.0
2.0
μs
Bus Wake-up Deglitcher
tPROPWL
30
50
150
μs
Bus Wake-up Event Reported(32)
tWAKE
—20
μs
Notes
28.
VSUP from 7.0 to 18 V, bus load R0 and C0 1.0 nF/1.0 kΩ, 6.8 nF/660 Ω, 10 nF/500 Ω. Measurement thresholds: 50% of TXD signal
to LIN signal threshold defined at each parameter.
29.
30.
31.
Measured between LIN signal threshold VIL or VIH and 50% of RXD signal.
32.
tWAKE is typically 2 internal clock cycles after LIN rising edge detected. See Figure 9 and Figure 8, page 17. In Sleep mode the VDD
rise time is strongly dependent upon the decoupling capacitor at VDD pin.
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