參數(shù)資料
型號(hào)： MPC106ARX83DG
廠商： MOTOROLA INC
元件分類： 總線控制器
英文描述： PCI Bridge/Memory Controller
中文描述： PCI BUS CONTROLLER, CBGA304
封裝： 21 X 25 MM, 3.16 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-304
文件頁(yè)數(shù)： 27/28頁(yè)
文件大?。?/td> 158K
代理商： MPC106ARX83DG
MPC106 PCI Bridge/Memory Controller Hardware Specifications
27
Document Revision History
1.9 Document Revision History
Table 15 lists significant changes between revisions of this document.
Table 15. Document Revision History
Document
Revision
Substantive Change(s)
Rev 0
Initial release
Rev 1
Changed VCO maximum frequency in Table 6 to 200 MHz
Changed input and Hi-Z leakage current in Table 4. from 10μA to 15μA
Changed I
and I
in Table 4 from 18mA and 14mA respectively to -7mA and 7mA to correct
the sign and reduce the current to worst case value for the lowest strength default driver
Changed footnote 4 to Table 6 to be consistent with SYSCLK jitter spec of 200ps
Modified Table 7, Figure 3, Table 8, and Figure 5 to clarify reference clock (60x Bus Clock or
SYSCLK) for input and output specifications
Changed Group I and Group II signals input setup requirement for 83 MHz in Table 7 from 3.0 ns
to 3.5 ns min.
Changed Group I-IV (non-PCI signals) input hold requirement (Spec 11a) in Table 7 from 1.0 ns
to 0 ns
Changed Group V and VI (PCI signals) input hold requirement (Spec 11b) in Table 7 from 1.0ns
to -0.5ns
Changed output valid times for all non-PCI signals (Specs 13a, 13b and 14a) from 8 ns to 7 ns at
66 Mhz and from 7 ns to 6 ns at 83 MHz
Corrected Figure 10 to reflect TOE signal is shared with DBG1 on pin U5
Rev 2
Changed input and Hi-Z leakage current, V
in
in Table 4 from 5.5V to 3.3V
Changed the power consumption data in Table 5
Changed note 7 of Table 8 to show the minimum timing specification assumes CL=0 pF
Rev 3
Deleted PLL[0-3] = 0010 from Table 11 to remove 1:1 mode operation between 16MHz and
25MHz
Added note 10 to Table 8 regarding PCI hold time
Lowered PCI 3.3V signalling output high voltage from 3.0 V to 2.7V and added current conditions
for PCI 3.3V VOH and VOL in Table 4 to reflect current production test
Included note 12 in Specification 10c of Table 4; Clarified note 9 in Table 8 and included in
Specification 12 and 18; Added a similar “guaranteed by design and not tested” note to Table 9
and included in Specifications 3, 7, and 11. All to reflect current production test.
Corrected Figure 12 dimensions from TBD to actual die size
Table 1 and Table 2 include notes on extended temperature parts.
Rev 4
Table 8, Note 8 changed to include: “These values are guaranteed by design and are not tested.”
Rev 5
Added PNS references below Table 1 and Table 6. Changed footnote ordering in Table 8,
Table 9, and Table 10. Added new footnote 2 to Table 6. Changed part number key.
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