參數(shù)資料
型號(hào): MPC5125YVN200
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 200 MHz, MICROCONTROLLER, PBGA324
封裝: 23 X 23 MM, 2.25 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, MS-034AJJ-1, TEPBGA-324
文件頁數(shù): 52/92頁
文件大?。?/td> 640K
代理商: MPC5125YVN200
MPC5125 Microcontroller Data Sheet, Rev. 3
Electrical and Thermal Characteristics
Freescale Semiconductor
56
4.3.6.1
Non-MUXed Mode
4.3.6.1.1
Non-MUXed Non-Burst Mode
Figure 14. Timing Diagram — Non-MUXed non-Burst Mode
t19 Non-MUXed mode page burst: ADDR cycle
tLPCck – tOD
tLPCck
ns
A7.20
t20 Non-MUXed mode page burst: burst DATA
(rd) input setup before next ADDR cycle
tOD + t6
ns
A7.21
t21 Non-MUXed mode page burst: burst DATA
(rd) input hold after next ADDR cycle
0—
ns
A7.22
t22 MUXed mode: non-burst CS[x] pulse width
(ALT × (AL
× 2) + WS)
× tLPCck
(ALT × (AL
× 2) + WS)
× tLPCck
ns
A7.23
t23 MUXed mode: read-burst CS[x] pulse
width
(ALT × (AL
× 2) + WS) +
BBT/DS) × tLPCck
(ALT × (AL
× 2) + WS) +
BBT/DS) × tLPCck
ns
A7.23
t24 MUXed mode: write-burst CS[x] pulse
width
(ALT × (AL
× 2) + 2.5 WS) +
BBT/DS)× tLPCck
(ALT × (AL
× 2) + 2.5 WS) +
BBT/DS)× tLPCck
ns
A7.23
Table 25. LPC Timing (continued)
Sym
Description
Min
Max
Units
SpecID
ADDR
DATA (rd)
CS[x]
R/W
DATA (wr)
OE
t6
t7
TS
TSIZ[1:0]
ACK
t1
LPC CLK
t4
tLPCck
t2
t3
t5
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