參數(shù)資料
型號: MPC5125YVN200
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 200 MHz, MICROCONTROLLER, PBGA324
封裝: 23 X 23 MM, 2.25 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, MS-034AJJ-1, TEPBGA-324
文件頁數(shù): 62/92頁
文件大小: 640K
代理商: MPC5125YVN200
Electrical and Thermal Characteristics
MPC5125 Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
65
Figure 28. Ethernet Timing Diagram — MII Tx Signal
Figure 29. Ethernet Timing Diagram — MII Async
Table 31. MII Async Signal Timing
Sym
Description
Min
Max
Unit
SpecID
t17
CRS, COL minimum pulse width
1.5
TX_CLK Period
A11.17
Table 32. MII Serial Management Channel Signal Timing
Sym
Description
Min
Max
Unit
SpecID
t18
MDC falling edge to MDIO output delay
0
25
ns
A11.18
t19
MDIO (input) to MDC rising edge setup
10
ns
A11.19
t20
MDIO (input) to MDC rising edge hold
0
ns
A11.20
t21
MDC pulse width high1
NOTES:
1 MDC is generated by the MPC5125 with a duty cycle of 50% except when MII_SPEED in the FEC MII_SPEED control register
is changed during operation. See the MPC5125 Reference Manual (MPC5125RM).
160
ns
A11.21
t22
MDC pulse width low1
160
ns
A11.22
t23
MDC period2
2 The MDC period must be set to a value of less than or equal to 2.5 MHz (to be compliant with the IEEE MII characteristic) by
programming the FEC MII_SPEED control register. See the MPC5125 Reference Manual (MPC5125RM).
400
ns
A11.23
t12, t16
t11, t15
t9, t13
TX_CLK (Input)
TXD[3:0] (Outputs)
TX_EN
TX_ER
t10, t14
t17
CRS, COL
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