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參數(shù)資料
| 型號： | MPC5125YVN200 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 200 MHz, MICROCONTROLLER, PBGA324 |
| 封裝： | 23 X 23 MM, 2.25 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, MS-034AJJ-1, TEPBGA-324 |
| 文件頁數(shù)： | 82/92頁 |
| 文件大?。?/td> | 640K |
| 代理商： | MPC5125YVN200 |
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System Design Information
MPC5125 Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
83
5.4
Pullup/Pulldown Resistor Requirements
The MPC5125 requires external pullup or pulldown resistors on certain pins.
5.4.1
Pulldown Resistor Requirements for TEST Pin
The MPC5125 requires a pulldown resistor on the test pin TEST.
5.5
JTAG
The MPC5125 has an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also provides a common on-chip
processor (COP) interface, which shares the IEEE 1149.1 JTAG port.
The COP interface provides access to the MPC5125’s embedded e300 processor and to other on-chip resources. This interface
provides a means for executing test routines and for performing software development and debug functions.
5.5.1
JTAG_TRST
Boundary scan testing is enabled through the JTAG interface signals. The JTAG_TRST signal is optional in the IEEE 1149.1
specification but is provided on all processors that implement the Power Architecture. To obtain a reliable power-on reset
performance, the JTAG_TRST signal must be asserted during power-on reset.
5.5.1.1
TRST and PORESET
The JTAG interface can control the direction of the MPC5125 I/O pads via the boundary scan chain. The JTAG module must
be reset before the MPC5125 comes out of power-on reset; do this by asserting TRST before PORESET is released.
For more details, see the Reset and JTAG Timing Specification.
Figure 50. PORESET vs. TRST
5.5.2
e300 COP/BDM Interface
There are two possibilities to connect the JTAG interface: using it with a COP connector and without a COP connector.
5.5.2.1
Boards Interfacing the JTAG Port via a COP Connector
The MPC5125 functional pin interface and internal logic provides access to the embedded e300 processor core through the
Freescale standard COP/BDM interface. Table 49 gives the COP/BDM interface signals. The pin order shown reflects only the
COP/BDM connector order.
TRST
PORESET
Required assertion of TRST
Optional assertion of TRST
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MPC5125YVN400 | 功能描述:微處理器 - MPU POWERPC EMBEDDED SOC SOC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC5125YVN400 | 制造商:Freescale Semiconductor 功能描述:ICMICROPROCESSOR32-BITCMOSPBGA324PI |
| MPC5125YVN400R | 制造商:Freescale Semiconductor 功能描述:POWERPC EMBEDDED SOC - Tape and Reel |
| MPC5200 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Hardware Specifications |
| MPC5200B | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SDRAM/DDR Memory Controller |
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