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參數(shù)資料
| 型號： | MPC603EFE133LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 133 MHz, RISC PROCESSOR, CQFP240 |
| 封裝： | 32 X 32 MM, 0.50 MM PITCH, WIRE BOND, CERAMIC, QFP-240 |
| 文件頁數(shù)： | 30/32頁 |
| 文件大?。?/td> | 149K |
| 代理商： | MPC603EFE133LX |
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PID6-603e Hardware Specifications, Rev 2
7
1.4.2 AC Electrical Characteristics
This section provides the AC electrical characteristics for the 603e. After fabrication, parts are sorted by
maximum processor core frequency as shown in Section 1.4.2.1, “Clock AC Specications” and tested for
conformance to the AC specications for that frequency. These specications are for 100 and 133.33 MHz
processor core frequencies. The processor core frequency is determined by the bus (SYSCLK) frequency
and the settings of the PLL_CFG[0–3] signals. Parts are sold by maximum processor core frequency; see
Section 1.10, “Ordering Information.”
1.4.2.1 Clock AC Specications
Table 6 provides the clock AC timing specications as dened in Figure 1.
Table 6. Clock AC Timing Specifications
At recommended operating conditions. See Table 2.
Num
Characteristic
100 MHz
133.33 MHz
Unit
Notes
Min
Max
Min
Max
Processor frequency
50
100
50
133.33
MHz
1
VCO frequency
100
266.66
100
266.66
MHz
1
SYSCLK (bus) frequency
16.67
66.67
16.67
66.67
MHz
1
SYSCLK cycle time
15.0
60.0
15.0
60.0
ns
2,3
SYSCLK rise and fall time
—
2.0
—
2.0
ns
2
4
SYSCLK duty cycle measured at 1.4 V
40.0
60.0
40.0
60.0
%
3
SYSCLK jitter
—
±150
—
±150
ps
4
Internal PLL relock time
—
100
—
100
s
3, 5
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the resulting
SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their
respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0–3] signal description in
Section 1.8, “System Design Information,” for valid PLL_CFG[0–3] settings.
2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. Cycle-to-cycle jitter, and is guaranteed by design.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the
maximum amount of time required for PLL lock after a stable Vdd and SYSCLK are reached during the
power-on reset sequence. This specication also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a
minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
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