參數(shù)資料
型號: MPC603PFE233LX
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 233 MHz, RISC PROCESSOR, CQFP240
封裝: 32 X 32 MM, 4.15 MM HEIGHT, 0.50 MM PITCH, WIRE BOND, CERAMIC, QFP-240
文件頁數(shù): 4/40頁
文件大小: 156K
代理商: MPC603PFE233LX
12
PID7v-603e Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
19
SYSCLK to ARTRY precharge enable
0.2 *
tsysclk
+ 1.0
0.2 *
tsysclk
+ 1.0
ns
2, 4, 7
20
Maximum delay to ARTRY precharge
1.0
1.0
tsysclk 4, 7
21
SYSCLK to ARTRY high impedance after precharge
2.0
2.0
tsysclk 5,7
Notes:
1. All output specications are measured from the 1.4 V of the rising edge of SYSCLK to the TTL level (0.8 V or
2.0 V) of the signal in question. Both input and output timings are measured at the pin (see Figure 4).
2. This minimum parameter assumes CL = 0 pF.
3. SYSCLK to output valid (5.5 V to 0.8 V) includes the extra delay associated with discharging the external
voltage from 5.5 V to 0.8 V instead of from Vdd to 0.8 V (5-V CMOS levels instead of 3.3-V CMOS levels).
4. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table
must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the
parameter in question.
5. Output signal transitions from GND to 2.0 V or Vdd to 0.8 V.
6. Nominal precharge width for ABB and DBB is 0.5 tsysclk.
7. Nominal precharge width for ARTRY is 1.0 tsysclk.
Table 8. Output AC Timing Specifications1 (Continued)
Vdd = AVdd = 2.5
± 5% V dc, OVdd = 3.3 ± 5%, GND = 0 V dc, 0 ≤ Tj ≤ 105 °C, CL = 50 pF (unless otherwise noted)
Num
Characteristic
160, 166, 180,
200 MHz
220, 225, 233,
240 MHz
Unit
Notes
Min
Max
Min
Max
相關(guān)PDF資料
PDF描述
MPC603PRX225LX 32-BIT, 225 MHz, RISC PROCESSOR, CBGA255
MPC603PFE240LX 32-BIT, 240 MHz, RISC PROCESSOR, CQFP240
MPC603RRX266LX 32-BIT, 266 MHz, RISC PROCESSOR, CBGA255
MPC603RRX300TX 32-BIT, 300 MHz, RISC PROCESSOR, CBGA255
MPC603RRX200LX 32-BIT, 200 MHz, RISC PROCESSOR, CBGA255
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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