參數(shù)資料
型號(hào): MPC603PFE233LX
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 233 MHz, RISC PROCESSOR, CQFP240
封裝: 32 X 32 MM, 4.15 MM HEIGHT, 0.50 MM PITCH, WIRE BOND, CERAMIC, QFP-240
文件頁(yè)數(shù): 6/40頁(yè)
文件大?。?/td> 156K
代理商: MPC603PFE233LX
14
PID7v-603e Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
1.4.3 JTAG AC Timing Specications
Table 9 provides the JTAG AC timing specications as dened in Figure 5, Figure 6, Figure 7 and Figure 8.
Table 9. JTAG AC Timing Specifications
Vdd = AVdd = 2.5
± 5% V dc, OVdd = 3.3 ± 5%, GND = 0 V dc, 0 ≤ Tj ≤ 105° C, C
L = 50 pF
Num
Characteristic
Min
Max
Unit
Notes
TCK frequency of operation
0
16
MHz
1
TCK cycle time
62.5
ns
2
TCK clock pulse width measured at 1.4 V
25
ns
3
TCK rise and fall times
0
3
ns
4
TRST setup time to TCK rising edge
13
ns
1
5
TRST assert time
40
ns
6
Boundary scan input data setup time
6
ns
2
7
Boundary scan input data hold time
27
ns
2
8
TCK to output data valid
4
25
ns
3
9
TCK to output high impedance
3
24
ns
3
10
TMS, TDI data setup time
0
ns
11
TMS, TDI data hold time
25
ns
12
TCK to TDO data valid
4
24
ns
13
TCK to TDO high impedance
3
15
ns
Notes:
1. TRST is an asynchronous signal. The setup time is for test purposes only.
2. Non-test signal input timing with respect to TCK.
3. Non-test signal output timing with respect to TCK.
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PDF描述
MPC603PRX225LX 32-BIT, 225 MHz, RISC PROCESSOR, CBGA255
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