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參數(shù)資料
| 型號： | MPC7400RX400TX |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 23/44頁 |
| 文件大小： | 744K |
| 代理商： | MPC7400RX400TX |
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MPC7400 RISC Microprocessor Hardware Specications
3
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Overview
Figure 1. MPC7400 Block Diagram
Additional
Features
Time
Base
Counter/
Decrementer
Clock
Multiplier
JTAG/COP
Interface
Power
Management
+
Fetcher
Branch
Processing
BTIC
(64
Entry)
+
x
÷
FPSCR
VSCR
FPSCR
L2CR
CTR
LR
PA
EA
+
x
÷
Instruction
Unit
Instruction
Queue
(6
Word)
2
Instructions
Reservation
Integer
System
Dispatch
Unit
64-Bit
(2
Instructions)
128-Bit
(4
Instructions)
32-Bit
Floating-
Point
Unit
32-Bit
64-Bit
Reservation
Load/Store
Unit
(EA
Calculation)
Finished
Stores
32-Bit
Completion
Unit
Reorder
Buffer
(8
Entry)
Tags
32-Kbyte
D
Cache
Bus
Interface
Unit
Instruction
Data
Reload
L2
Controller
L2
Tags
L2
Bus
Interface
Unit
L2
Castout
32-Bit
60x/MAX
Address
Bus
64-Bit
60x
Data
Bus/128-Bit
MAX
Data
Bus
19-Bit
L2
Address
Bus
64-/128-Bit
L2
Data
Bus
Integer
Station
Reservation
Station
Reservation
Station
Register
Unit
1
Unit
2
Reservation
Station
FPR
File
6
Rename
Buffers
Reservation
Station
(2
Entry)
GPR
File
6
Rename
Buffers
VCIU
Vector
ALU
Reservation
Station
Reservation
Station
Permute
VR
File
6
Rename
Buffers
Unit
64-Bit
Reload
Table
VSIU
VFPU
128-Bit
Ability
to
complete
up
Completed
Stores
Instruction
MMU
SRs
(Shadow)
128-Entry
IBAT
Array
ITLB
BHT
(512
Entry)
L2
Miss
L2
Data
Transaction
Table
Tags
32-Kbyte
iCache
Data
Reload
Queue
Instruction
Reload
Queue
Load
Fold
L1Operations
to
two
instructions
per
clock
Data
MMU
SRs
(Original)
128-Entry
DBAT
Array
DTLB
Queue
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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