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參數(shù)資料
| 型號： | MPC7400RX400TX |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 41/44頁 |
| 文件大?。?/td> | 744K |
| 代理商： | MPC7400RX400TX |
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MPC7400 RISC Microprocessor Hardware Specications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features
Memory management unit
— 128 entry, 2-way set associative instruction TLB
— 128 entry, 2-way set associative data TLB
— Hardware reload for TLBs
— 4 instruction BATs and 4 data BATs
— Virtual memory support for up to 4 exabytes (252) of virtual memory
— Real memory support for up to 4 gigabytes (232) of physical memory
— Snooped and invalidated for TLBI instructions
Efcient data ow
— All data buses between VRF, load/store unit, dL1, iL1, L2, and the bus are 128-bits wide
— dL1 is fully pipelined to provide 128 bits/cycle to/from the VRF
— L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s
— Up to 8 outstanding, out-of-order, cache misses between dL1 and L2/bus
— Up to 7 outstanding, out-of-order transactions on the bus
— Load folding to fold new dL1 misses into older, outstanding load and store misses to the same
line
— Store miss merging for multiple store misses to the same line. Only coherency action taken (i.e.,
address only) for store misses merged to all 32 bytes of a cache line (no data tenure needed).
— 2-entry nished store queue and 4-entry completed store queue between load/store unit and dL1
— Separate additional queues for efcient buffering of outbound data (castouts, write throughs,
etc.) from dL1 and L2
Bus interface
— New MPX bus extension to 60X processor interface
— Mode-compatible with 60x processor interface
— 32-bit address bus
— 64 bit data bus
— Bus-to-core frequency multipliers of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x,
8x supported
— Selectable interface voltages of 1.8 and 3.3V.
Power management
— Low-power design with thermal requirements very similar to MPC740 and MPC750.
— 1.8 volt processor core
— Selectable interface voltages below 3.3V can reduce power in output buffers
— Three static power saving modes: doze, nap, and sleep
— Dynamic power management
Testability
— LSSD scan design
— IEEE 1149.1 JTAG interface
— Array built-in self test (ABIST)—factory test only.
— Redundancy on L1 data arrays and L2 tag arrays
Reliability and serviceability
— Parity checking on 60x and L2 cache buses
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For More Information On This Product,
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