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參數(shù)資料
| 型號： | MPC8245TZU300D |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 20/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 300MHZ 352-TBGA |
| 標準包裝： | 24 |
| 系列： | MPC82xx |
| 處理器類型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 300MHz |
| 電壓： | 1.8V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 352-LBGA |
| 供應商設備封裝： | 352-TBGA（35x35） |
| 包裝： | 托盤 |
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MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
27
Electrical and Thermal Characteristics
Figure 16. I2C AC Test Load
Noise margin at the HIGH level for each connected device (including
hysteresis)
VNH
0.2
× OVDD
—V
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I
2C timing (I2)
with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high
(H) state or setup time. Also, tI2SXKL symbolizes I
2C timing (I2) for the time that the data with respect to the start condition
(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I
2C
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. As a transmitter, the MPC8245 provides a delay time of at least 300 ns for the SDA signal (referred to as the Vihmin of the
SCL signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition.
When the MPC8245acts as the I2C bus master while transmitting, it drives both SCL and SDA. As long as the load on SCL
and SDA is balanced, the MPC8245 does not cause the unintended generation of a Start or Stop condition. Therefore, the
300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required
for the MPC8245 as transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register to ensure
both the desired I2C SCL clock frequency and SDA output delay time are achieved. It is assumed that the desired I2C SCL
clock frequency is 400 KHz and the digital filter sampling rate register (DFFSR bits in I2CFDR) is programmed with its default
setting of 0x10 (decimal 16):
SDRAM Clock Frequency
100 MHz
133 MHz
FDR Bit Setting
0x00
0x2A
Actual FDR Divider Selected
384
896
Actual I2C SCL Frequency Generated
260.4 KHz 148.4 KHz
For details on I2C frequency calculation, refer to the application note AN2919 “Determining the I2C Frequency Divider Ratio
for SCL”.
3. The maximum tI2DXKL has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
4. Guaranteed by design.
Table 13. I2C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 12).
Parameter
Symbol 1
Min
Max
Unit
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
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