- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4063 > MPC8245TZU300D (Freescale Semiconductor)IC MPU 32BIT 300MHZ 352-TBGA PDF資料下載
參數(shù)資料
| 型號： | MPC8245TZU300D |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 58/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 300MHZ 352-TBGA |
| 標準包裝： | 24 |
| 系列： | MPC82xx |
| 處理器類型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 300MHz |
| 電壓： | 1.8V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 352-LBGA |
| 供應商設(shè)備封裝： | 352-TBGA（35x35） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁當前第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
61
Document Revision History
0.1
—
Made VDD/AVDD/AVDD2 = 1.8 V ± 100 mV information for 133-MHz memory interface operation to
Section 1.3, Table 2, Table 5, Table 9, Table 17, and Section 1.7.2.
Pin D17, formerly LAVDD (supply voltage for DLL), is a NC on the MPC8245 since the DLL voltage is
supplied internally. Eliminated all references to LAVDD; updated Section 1.7.1.
Previous Note 4 of Table 2 did not apply to the MPC8245 (MPC8240 document legacy). New Note 4
added in reference to maximum CPU speed at reduced VDD voltage.
Updated the Programmable Output Impedance of DEV_MEM_ADDR in Table 4 to 6
Ω to reflect
characterization data.
Updated Table 5 to reflect reduced power consumption when operating VDD/AVDD/AVDD2 = 1.8 V ±
100 mV. Changed Notes 2, 3, and 4 to reflect VDD at 1.9 V. Changed Note 5 to represent VDD = AVDD
= 1.8 V.
Updated Table 7 to reflect VDD/AVDD/AVDD2 voltage level operating frequency dependencies;
changed 250 MHz device column to 266 MHz; modified Note 1 eliminating VCO references; added
Note 2. Changed 250 MHz processor frequency offering to 266 MHz.
Changed Spec 12b for memory output valid time in Table 11 from 5.5 ns to 4.5 ns; this is a key
specification change to enable 133-MHz memory interface designs.
Updated Pinout Table 16 with the following changes:
Pin types for RCS0, RCS3/TRIG_OUT and DA[11:15] were erroneously listed as I/O, changed Pin
Types to Output.
Pin types for REQ4/DA4, RCS2/TRIG_IN, and PLL_CFG[0:4]/DA[10:6] were erroneously listed as
Input, changed Pin Types to I/O.
Changed Pin D17 from LAVDD to No Connect; deleted Note 21 and references.
Notes 3, 5, and 7 contained references to the MPC8240 (MPC8240 document legacy); changed
these references to MPC8245.
Previous Notes 13 and 14 did not apply to the MPC8245 (MPC8240 document legacy), these notes
were deleted; moved Note 19 to become new Note 13; moved Note 20 to become new Note 14;
updated associated references.
Added Note 3 to SDMA[1:0] signals about internal pull-up resistors during reset state.
Reversed vector ordering for the PCI Interface Signals: C/BE[0:3] changed to C/BE[3:0], AD[0:31]
changed to AD[31:0], GNT[0:3] changed to GNT[3:0], and REQ[0:3] changed to REQ[3:0]. The
package pin number orderings were also reversed meaning that pin functionality did NOT change.
For example, AD0 is still on signal C22, AD1 is still on signal D22,..., AD31 is still on signal V25. This
change was made to make the vectored PCI signals in this hardware specification consistent with
the PCI Local Bus Specification and the MPC8245 Integrated Processor Reference Manual vector
ordering.
Changed TEST1/DRDY signal on pin B20 to DRDY.
Changed TEST2 signal on pin Y2 to RTC for performance monitor use.
Updated PLL Table 17 with the following changes for 133-MHz memory interface operation:
Added Ref. 9 (01001) and Ref. 17 (10111) details; removed these settings from Note 10 (reserved
settings list).
Enhanced range of Ref. 10 (10000).
Updated Note 13, changed bits 16–20 erroneous information to correct bits 23–19.
Added Notes 16 and 17.
Added information to Section 1.7.8 in reference to CHKSTOP_IN and SRESET being unavailable in
extended ROM mode.
0.0
—
Initial release.
Table 19. Revision History Table (continued)
Revision
Date
Substantive Change(s)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC8245TVV300D | IC MPU 32BIT 300MHZ PPC 352-TBGA |
| MPC8378VRANGA | MPU POWERQUICC II 800MHZ 689PBGA |
| MPC8377VRANGA | MPU POWERQUICC II 800MHZ 689PBGA |
| MPC866TVR100A | IC MPU POWERQUICC 100MHZ 357PBGA |
| IDT709159L7BF | IC SRAM 72KBIT 7NS 100FBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8245TZU333D | 功能描述:微處理器 - MPU 333MHz 632.7MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8245TZU350D | 功能描述:微處理器 - MPU 350MHz 665MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8247 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MPC8272 PowerQUICC II Family Hardware Specifications |
| MPC8247CVR | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MPC8272 PowerQUICC II Family Hardware Specifications |
| MPC8247CVRB | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
發(fā)布緊急采購，3分鐘左右您將得到回復。