This table provides the DDR capacitan" />
參數(shù)資料
型號: MPC8313E-RDB
廠商: Freescale Semiconductor
文件頁數(shù): 8/99頁
文件大?。?/td> 0K
描述: BOARD PROCESSOR
產(chǎn)品培訓(xùn)模塊: MPC8313E PowerQUICC Processor
MPC8314/15 Product Overview
標(biāo)準(zhǔn)包裝: 1
系列: PowerQUICC II™ PRO
類型: MCU
適用于相關(guān)產(chǎn)品: MPC8313E
所含物品: 參考設(shè)計(jì)板、軟件和說明文檔
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MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
16
Freescale Semiconductor
This table provides the DDR capacitance when GVDD(typ) = 2.5 V.
This table provides the current draw characteristics for MVREF.
6.2
DDR and DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1
DDR and DDR2 SDRAM Input AC Timing Specifications
This table provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ) = 1.8 V.
Output leakage current
IOZ
–9.9
A4
Output high current (VOUT = 1.95 V)
IOH
–16.2
mA
Output low current (VOUT = 0.35 V)
IOL
16.2
mA
Note:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V
V
OUT GVDD.
Table 15. DDR SDRAM Capacitance for GVDD(typ) = 2.5 V
Parameter/Condition
Symbol
Min
Max
Unit
Note
Input/output capacitance: DQ, DQS
CIO
68
pF
1
Delta input/output capacitance: DQ, DQS
CDIO
—0.5
pF
1
Note:
1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA =25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
Table 16. Current Draw Characteristics for MVREF
Parameter/Condition
Symbol
Min
Max
Unit
Note
Current draw for MVREF
IMVREF
—500
A1
Note:
1. The voltage regulator for MVREF must be able to supply up to 500 A current.
Table 17. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
At recommended operating conditions with GVDD of 1.8 ± 5%.
Parameter
Symbol
Min
Max
Unit
Note
AC input low voltage
VIL
—MVREF – 0.25
V
AC input high voltage
VIH
MVREF + 0.25
V
Table 14. DDR SDRAM DC Electrical Characteristics for GVDD(typ) = 2.5 V (continued)
Parameter/Condition
Symbol
Min
Max
Unit
Note
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