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型號(hào)：	MPC8313E-RDB
廠商：	Freescale Semiconductor
文件頁(yè)數(shù)：	92/99頁(yè)
文件大?。?/td>	0K
描述：	BOARD PROCESSOR
產(chǎn)品培訓(xùn)模塊：	MPC8313E PowerQUICC Processor MPC8314/15 Product Overview
標(biāo)準(zhǔn)包裝：	1
系列：	PowerQUICC II™ PRO
類型：	MCU
適用于相關(guān)產(chǎn)品：	MPC8313E
所含物品：	參考設(shè)計(jì)板、軟件和說(shuō)明文檔
相關(guān)產(chǎn)品：	MPC8313VRAFFB-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313EZQAFFB-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313EVRAFFB-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313ECZQAFFB-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313ECVRAFFB-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313CZQAFFB-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313CVRAFFB-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313ZQAFF-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313ZQADD-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313VRAFF-ND - IC MPU POWERQUICC II PRO 516PBGA 更多...

MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

The COP function of these processors allows a remote computer system (typically, a PC with dedicated

hardware and debugging software) to access and control the internal operations of the processor. The COP

interface connects primarily through the JTAG port of the processor, with some additional status

monitoring signals. The COP port requires the ability to independently assert TRST without causing

PORESET. If the target system has independent reset sources, such as voltage monitors, watchdog timers,

power supply failures, or push-button switches, then the COP reset signals must be merged into these

signals with logic.

The arrangement shown in Figure 61 allows the COP to independently assert HRESET or TRST, while

ensuring that the target can drive HRESET as well. If the JTAG interface and COP header are not used,

TRST should be tied to PORESET so that it is asserted when the system reset signal (PORESET) is

asserted.

The COP header shown in Figure 61 adds many benefits—breakpoints, watchpoints, register and memory

examination/modification, and other standard debugger features are possible through this interface—and

can be as inexpensive as an unpopulated footprint for a header to be added when needed.

The COP interface has a standard header for connection to the target system, based on the 0.025"

square-post, 0.100" centered header assembly (often called a Berg header).

There is no standardized way to number the COP header shown in Figure 61; consequently, many different

pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then

left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter

clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in

Figure 61 is common to all known emulators.

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
MPC8313E-RDBB	功能描述:開發(fā)板和工具包 - 其他處理器 CPU BOARD VER 2.1 RoHS:否制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
MPC8313E-RDBB	制造商:Freescale Semiconductor 功能描述:; LEADED PROCESS COMPATIBLE:YES; PEAK RE
MPC8313E-RDBC	功能描述:開發(fā)板和工具包 - 其他處理器 8313E CPU board Ver 2.2 RoHS:否制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
MPC8313EVRADD	制造商:Freescale Semiconductor 功能描述:MPC83XX RISC 32-BIT 90NM 333MHZ 1V/1.8V/2.5V/3.3V 516-PIN TE - Trays
MPC8313EVRADDB	功能描述:微處理器 - MPU PBGA W/ ENCR RoHS:否制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324

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