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參數(shù)資料
型號(hào): MPC8313E-RDB
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 87/99頁(yè)
文件大?。?/td> 0K
描述: BOARD PROCESSOR
產(chǎn)品培訓(xùn)模塊: MPC8313E PowerQUICC Processor
MPC8314/15 Product Overview
標(biāo)準(zhǔn)包裝: 1
系列: PowerQUICC II™ PRO
類型: MCU
適用于相關(guān)產(chǎn)品: MPC8313E
所含物品: 參考設(shè)計(jì)板、軟件和說(shuō)明文檔
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MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
88
Freescale Semiconductor
22.2
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1,
AVDD2, and SDAVDD, respectively). The AVDD level should always be equivalent to VDD, and preferably
these voltages are derived directly from VDD through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits as illustrated in Figure 58, one to each of the five AVDD pins. By
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum effective series inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD
pin, which is on the periphery of package, without the inductance of vias.
This figure shows the PLL power supply filter circuits.
Figure 58. PLL Power Supply Filter Circuit
The SDAVDD signal provides power for the analog portions of the SerDes PLL. To ensure stability of the
internal clock, the power supplied to the PLL is filtered using a circuit like the one shown in Figure 59.
For maximum effectiveness, the filter circuit should be placed as closely as possible to the SDAVDD ball
to ensure it filters out as much noise as possible. The ground connection should be near the SDAVDD ball.
The 0.003-F capacitor is closest to the ball, followed by the two 2.2-F capacitors, and finally the 1-
resistor to the board supply plane. The capacitors are connected from traces from SDAVDD to the ground
plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be
kept short, wide, and direct.
Figure 59. SerDes PLL Power Supply Filter Circuit
Note the following:
SDAVDD should be a filtered version of XCOREVDD.
VDD
AVDD1 and AVDD2
10
2.2 F
Low ESL Surface Mount Capacitors
Note:
1. An 0805 sized capacitor is recommended for system initial bring-up.
XCOREVDD
SDAVDD
SDAVSS
2.2 F1
0.003 F
1.0
2.2 F1
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