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參數(shù)資料
| 型號： | MPC8349CZUAJFB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 22/87頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU POWERQUICC II PRO 672TBGA |
| 標準包裝： | 24 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 533MHz |
| 電壓： | 1.2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 672-LBGA |
| 供應商設(shè)備封裝： | 672-TBGA（35x35） |
| 包裝： | 托盤 |
| 配用： | MPC8349E-MITX-GP-ND - KIT REFERENCE PLATFORM MPC8349E MPC8349E-MITXE-ND - BOARD REFERENCE FOR MPC8349 MPC8349EA-MDS-PB-ND - KIT MODULAR DEV SYSTEM MPC8349E |
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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
Freescale Semiconductor
29
Ethernet: Three-Speed Ethernet, MII Management
Figure 15 shows the TBI receive AC timing diagram.
Figure 15. TBI Receive AC Timing Diagram
RXD[7:0], RX_DV, RX_ER (RCG[9:0]) setup time to rising
PMA_RX_CLK
tTRDVKH
2
2.5
—
ns
RXD[7:0], RX_DV, RX_ER (RCG[9:0]) hold time to rising
PMA_RX_CLK
tTRDXKH
2
1.5
—
ns
RX_CLK clock rise time (20%–80%)
tTRXR
0.7
—
2.4
ns
RX_CLK clock fall time (80%–20%)
tTRXF
0.7
—
2.4
ns
Notes:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH symbolizes TBI receive timing
(TR) with respect to the time data input signals (D) reach the valid state (V) relative to the tTRX clock reference (K) going to
the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with respect to the time data input signals
(D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state. In general, the clock reference symbol
is based on three letters representing the clock of a particular function. For example, the subscript of tTRX represents the TBI
(T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). For
symbols representing skews, the subscript SK followed by the clock that is being skewed (TRX).
2. Setup and hold time of even numbered RCG are measured from the riding edge of PMA_RX_CLK1. Setup and hold times
of odd-numbered RCG are measured from the riding edge of PMA_RX_CLK0.
Table 30. TBI Receive AC Timing Specifications (continued)
At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
PMA_RX_CLK1
RCG[9:0]
tTRX
tTRXH
tTRXR
tTRXF
tTRDVKH
PMA_RX_CLK0
tTRDXKH
tTRDVKH
tTRDXKH
tTRXH
Even RCG
Odd RCG
tSKTRX
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|---|---|
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