參數(shù)資料
型號： MPC8349CZUAJFB
廠商： Freescale Semiconductor
文件頁數(shù)： 67/87頁
文件大?。?/td> 0K
描述： IC MPU POWERQUICC II PRO 672TBGA
標準包裝： 24
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 533MHz
電壓： 1.2V
安裝類型： 表面貼裝
封裝/外殼： 672-LBGA
供應商設備封裝： 672-TBGA（35x35）
包裝： 托盤
配用： MPC8349E-MITX-GP-ND - KIT REFERENCE PLATFORM MPC8349E
MPC8349E-MITXE-ND - BOARD REFERENCE FOR MPC8349
MPC8349EA-MDS-PB-ND - KIT MODULAR DEV SYSTEM MPC8349E
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
Freescale Semiconductor
7
Electrical Characteristics
2.1.1
Absolute Maximum Ratings
Table 1 provides the absolute maximum ratings.
Table 1. Absolute Maximum Ratings1
Parameter
Symbol
Max Value
Unit
Notes
Core supply voltage
VDD
–0.3 to 1.32 (1.36 max
for 667-MHz core
frequency)
V—
PLL supply voltage
AVDD
–0.3 to 1.32 (1.36 max
for 667-MHz core
frequency)
V—
DDR and DDR2 DRAM I/O voltage
GVDD
–0.3 to 2.75
–0.3 to 1.98
V—
Three-speed Ethernet I/O, MII management voltage
LVDD
–0.3 to 3.63
V
—
PCI, local bus, DUART, system control and power management, I2C,
and JTAG I/O voltage
OVDD
–0.3 to 3.63
V
—
Input voltage
DDR DRAM signals
MVIN
–0.3 to (GVDD + 0.3)
V
2, 5
DDR DRAM reference
MVREF
–0.3 to (GVDD + 0.3)
V
2, 5
Three-speed Ethernet signals
LVIN
–0.3 to (LVDD + 0.3)
V
4, 5
Local bus, DUART, CLKIN, system control and
power management, I2C, and JTAG signals
OVIN
–0.3 to (OVDD + 0.3)
V
3, 5
PCI
OVIN
–0.3 to (OVDD + 0.3)
V
6
Storage temperature range
TSTG
–55 to 150
°C—
Notes:
1 Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2 Caution: MV
IN must not exceed GVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3 Caution: OV
IN must not exceed OVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4 Caution: LV
IN must not exceed LVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during power-on
reset and power-down sequences.
5 (M,L,O)V
IN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
6 OVIN on the PCI interface can overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as
shown in Figure 3.
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