參數(shù)資料
型號(hào): MPC8378EVRANFA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 333 MHz, MICROPROCESSOR, PBGA689
封裝: 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù): 105/125頁
文件大?。?/td> 894K
代理商: MPC8378EVRANFA
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
80
Figure 54. Differential Voltage Definitions for Transmitter or Receiver
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common
mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5 V and 2.0 V. Using these values,
the peak-to-peak voltage swing of each signal (TD or TD) is 500 mVp-p, which is referred as the single-ended swing for each
signal. In this example, since the differential signaling environment is fully symmetrical, the transmitter output’s differential
swing (VOD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500 mV
and –500 mV, in other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage
(VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p) is 1000 mVp-p.
20.2
SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding
SerDes lanes. The SerDes reference clocks inputs are SD1_REF_CLK and SD1_REF_CLK for both lanes of SerDes1, and
SD2_REF_CLK and SD2_REF_CLK for both lanes of SerDes2.
The following sections describe the SerDes reference clock requirements and some application information.
20.2.1
SerDes Reference Clock Receiver Characteristics
Figure 55 shows a receiver reference diagram of the SerDes reference clocks.
SerDes Reference Clock Receiver Reference Circuit Structure
—The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as shown in Figure 55.
Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a 50
termination to SGND_SRDSn
(xcorevss) followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the Differential Mode and
Single-ended Mode description below for further detailed requirements.
The maximum average current requirement that also determines the common mode voltage range
— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the
maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage
is not critical as long as it is within the range allowed by the maximum average current of 8 mA (refer to the
following bullet for more detail), since the input is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V
50 = 8 mA)
while the minimum common mode input level is 0.1 V above SGND_SRDSn (xcorevss). For example, a clock
Differential Swing, VID or VOD = A – B
A Volts
B Volts
SDn_TX or
SDn_RX
SDn_TX or
SDn_RX
Differential Peak Voltage, VDIFFp = |A – B|
Differential Peak-Peak Voltage, VDIFFpp = 2
VDIFFp (not shown)
Vcm = (A + B)/2
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