參數(shù)資料
型號(hào): MPC8378VRANGA
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 11/128頁(yè)
文件大?。?/td> 0K
描述: MPU POWERQUICC II 800MHZ 689PBGA
標(biāo)準(zhǔn)包裝: 27
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 800MHz
電壓: 1.05V
安裝類型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 689-TEPBGA II(31x31)
包裝: 托盤
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MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
108
Freescale Semiconductor
22 Clocking
This figure shows the internal distribution of clocks within this chip.
Figure 67. Clock Subsystem
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on
whether the device is configured in PCI host or PCI agent mode. When the device is configured as a PCI
host device, CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (
÷2) and the
multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input
selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICOEn]
parameters select whether CFG_CLKIN_DIV is driven out on the PCI_CLK_OUTn signals.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system, to allow the device to function. When the device
is configured as a PCI agent device, PCI_CLK is the primary input clock. When the device is configured
as a PCI agent device the CLKIN signal should be tied to GND.
Core PLL
System PLL
DDR
LBIU
LSYNC_IN
LSYNC_OUT
LCLK[0:2]
MCK[0:5]
core_clk
e300 core
csb_clk to rest
CLKIN
csb_clk
6
DDR
Memory
Local Bus
PCI_CLK[0:4]
PCI_SYNC_OUT
PCI_CLK/
Clock
Unit
of the device
ddr_clk
lbiu_clk
CFG_CLKIN_DIV
PCI Clock
PCI_SYNC_IN
Device
Memory
Device
/n
to local bus
memory
controller
to DDR
memory
controller
DLL
Clock
Div
/2
Divider
5
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