參數(shù)資料
型號： MPC8378VRANGA
廠商： Freescale Semiconductor
文件頁數(shù)： 32/128頁
文件大小： 0K
描述： MPU POWERQUICC II 800MHZ 689PBGA
標(biāo)準(zhǔn)包裝： 27
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 800MHz
電壓： 1.05V
安裝類型： 表面貼裝
封裝/外殼： 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 689-TEPBGA II（31x31）
包裝： 托盤
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
127
2
10/2009
In Table 3, “Recommended Operating Conditions,” added “Operating temperature range” values.
In Table 5, “Power Dissipation 1,” corrected maximal application for 800/400 MHz to 4.3 W.
In Table 5, “Power Dissipation 1,” added a column for “Typical Application at Tj =65°C (W)”.
In Table 5, “Power Dissipation 1,” added a column for “Sleep Power at Tj =65°C (W)”.
In Table 11, removed overbar from CFG_CLKIN_DIV.
In Table 17, “Current Draw Characteristics for MVREF,” updated IMVREF maximum value for both DDR1
and DDR2 to 600 and 400
μA, respectively. Also, updated Note 1 and added Note 2.
“Min” and “Max”. Footnote 2 updated to state “T is the MCK clock period”.
DDR2 SDRAM Output AC Timing Specifications,” clarified that the frequency parameters are data rates.
In Table 27, “SGMII DC Receiver Electrical Characteristics,” updated bit name LSTS to SEIC
x, the
parameter values, and the maximum value of SEIC
x = 01 to 100.
In Table 27, “SGMII DC Receiver Electrical Characteristics,” updated VLOS maximum value for LSTS =0
to 150 mV .
In Table 34, “RMII Transmit AC Timing Specifications,” updated tRMTDXI to 2.0 ns.
In Table 68, “TePBGA II Pinout Listing,” removed pin THERM0; it is now Reserved. Also added 1.05 V
to VDD pin.
In Table 70, “Operating Frequencies for TePBGA II,” corrected “DDR2 memory bus frequency (MCK)”
range to 125–200.
In Table 75, “e300 Core PLL Configuration,” added 3.5:1 and 4:1 core_clk: csb_clk ratio options.
In Table 76, “Example Clock Frequency Combinations,” updated column heading to “DDR data rate” .
In Section 19.2, “SPI AC Timing Specifications,” corrected tNIKHOX and tNEKHOX to tNIKHOV and tNEKHOV,
respectively.
1
02/2009
In Table 3, “Recommended Operating Conditions,” added two new rows for 800 MHz, and created two
rows for SerDes. In addition, changed 666 to 667 MHz.
In Table 5, “Power Dissipation 1,” added Notes 4 and 5. In addition, changed 666 to 667 MHz.
footnote to references to MVREF, MDQ, and MDQS, referencing AN3665,
MPC837xE Design Checklist.
In Table 21, updated tDDKHCX minimum value for 333 MHz to 2.40.
In Table 68, “TePBGA II Pinout Listing,” added footnote to USBDR_STP_SUSPEND and modified
footnote 10 and added footnote 15.
In Table 70, “Operating Frequencies for TePBGA II,” changed 667 to 800 MHz for
core_clk.
In Table 76, “Example Clock Frequency Combinations,” added 800 MHz cells for e300 core.
Updated part numbering information in AF column in Table 80, “Part Numbering Nomenclature.” In
addition, modified extended temperature information in notes 1 and 4.
In Table 81, “Available Parts (Core/DDR Data Rate),” added new row for 800/400 MHz.
0
12/2008 Initial public release.
Table 83. Document Revision History (continued)
Revision
Date
Substantive Change(s)
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