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| 型號： | MPC8379ECVRANGA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689 |
| 封裝： | 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689 |
| 文件頁數(shù)： | 28/114頁 |
| 文件大?。?/td> | 1337K |
| 代理商： | MPC8379ECVRANGA |
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MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
20
Freescale Semiconductor
DDR1 and DDR2 SDRAM
The minimum frequency for DDR2 is 250 MHz data rate (125 MHz clock), 167 MHz data rate (83 MHz
clock) for DDR1.
Figure 4 shows the DDR1 and DDR2 SDRAM output timing for the MCK to MDQS skew measurement
(tDDKHMH).
Figure 4. DDR Timing Diagram for tDDKHMH
MDQS epilogue end
tDDKHME
–0.6
0.6
ns
Note:
1 The symbols used for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2 All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3 ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ//MDM/MDQS.
4 Note that t
DDKHMH follows the symbol conventions described in Note 1. For example, tDDKHMH describes the DDR timing (DD)
from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control
of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in
the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same
adjustment value. See the
MPC8379E PowerQUICC II Pro Host Processor Reference Manual for a description and
understanding of the timing modifications enabled by use of these bits.
5 Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data MDQ, ECC, or
data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6 All outputs are referenced to the rising edge of MCKn at the pins of the microprocessor. Note that t
DDKHMP follows the symbol
conventions described in Note 1.
7 Clock Control register is set to adjust the memory clocks by 1/2 the applied cycle.
8 See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.
Table 20. DDR1 and DDR2 SDRAM Output AC Timing Specifications (continued)
Parameter
Symbol1
Min
Max
Unit
Notes
MDQS
MCK[n]
tMCK
tDDKHMHmax) = 0.6 ns
tDDKHMH(min) = –0.6 ns
MDQS
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|---|---|
| MPC8379ECZQAFDA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
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| MPC8379ECZQAFGA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
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