參數(shù)資料
型號(hào): MPC8379ECVRANGA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689
封裝: 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù): 88/114頁
文件大?。?/td> 1337K
代理商: MPC8379ECVRANGA
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
75
High-Speed Serial Interfaces (HSSI)
clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular
clock driver chip.
Figure 55. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
Figure 56 shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
It assumes the DC levels of the clock driver are compatible with device SerDes reference clock input’s DC
requirement.
Figure 56. Single-Ended Connection (Reference Only)
20.2.4
AC Requirements for SerDes Reference Clocks
The clock driver selected should provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100 KHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
50
Ω
50
Ω
SD
n_REF_CLK
SD
n_REF_CLK
Clock Driver
100
Ω differential PWB trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
LVPECL CLK Driver Chip
R2
R1
10 nF
MPC8379E
50
Ω
50
Ω
SD
n_REF_CLK
SD
n_REF_CLK
100
Ω differential PWB trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
Single-Ended CLK
Driver Chip
33
Ω
Total 50
Ω. Assume clock driver’s
output impedance is about 16
Ω.
50
Ω
MPC8379E
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