參數(shù)資料
型號(hào)： MPC8379ECVRANGA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689
封裝： 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù)： 44/114頁
文件大?。?/td> 1337K
代理商： MPC8379ECVRANGA
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
35
Local Bus
10.2
Local Bus AC Electrical Specifications
Table 38 describes the general timing parameters of the local bus interface of the device.
Table 38. Local Bus General Timing Parameters—PLL Enable Mode
Parameter
Symbol1
Min
Max
Unit
Notes
Local bus cycle time
tLBK
7.5
15
ns
Input setup to local bus clock (except LUPWAIT/LGTA)tLBIVKH
1.5
—
ns
Input hold from local bus clock
tLBIXKH
1.0
—
ns
LUPWAIT/LGTA input setup to local bus clock
tLBIVKH1
1.5
—
ns
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT1
1.5
—
ns
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT2
3—
ns
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT3
2.5
—
ns
Local bus clock to LALE rise
tLBKHLR
—4.5
ns
—
Local bus clock to output valid (except LALE)
tLBKHOV
—4.5
ns
Local bus clock to output high impedance for LAD/LDP
tLBKHOZ
—
3.8
ns
Output hold from local bus clock for LAD/LDP
tLBKHOX
1—
ns
Note:
1 The symbols used for timing specifications herein follow the pattern of t
(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for
clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to
the output (O) going invalid (X) or output hold time.
2 All timings are in reference to rising edge of LSYNC_IN at LBV
DD/2 and the 0.4 × LBVDD of the signal in question.
3 All signals are measured from LBV
DD/2 of the rising/falling edge of LSYNC_IN to 0.5 × LBVDD of the signal in question.
4 Input timings are measured at the pin.
5 t
LBOTOT1 should be used when LBCR[AHD] is not set and the load on LALE output pin is at least 10pF less than the load on
LAD output pins.
6 t
LBOTOT2 should be used when LBCR[AHD] is set and the load on LALE output pin is at least 10pF less than the load on LAD
output pins.
7 t
LBOTOT3 should be used when LBCR[AHD] is set and the load on LALE output pin equals to the load on LAD output pins.
8 For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
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