參數(shù)資料
型號(hào): MPC8533EVTANGA
廠商: Freescale Semiconductor
文件頁數(shù): 53/112頁
文件大?。?/td> 0K
描述: MPU POWERQUICC 783-PBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 800MHz
電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
45
Local Bus
Local bus clock to data valid for LAD/LDP
tLBKLOV2
1.6
ns
4
Local bus clock to address valid for LAD, and LALE
tLBKLOV3
1.6
ns
4
Output hold from local bus clock (except LAD/LDP and
LALE)
tLBKLOX1
–4.1
ns
4
Output hold from local bus clock for LAD/LDP
tLBKLOX2
–4.1
ns
4
Local bus clock to output high Impedance (except
LAD/LDP and LALE)
tLBKLOZ1
1.4
ns
7
Local bus clock to output high impedance for LAD/LDP
tLBKLOZ2
1.4
ns
7
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case
for clock one (1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect
to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to local bus clock for PLL bypass mode. Timings may be negative with respect to the local bus
clock because the actual launch and capture of signals is done with the internal launch/capture clock, which proceeds LCLK
by tLBKHKT.
3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BVDD/2.
4. All signals are measured from BVDD/2 of the rising edge of local bus clock for PLL bypass mode to 0.4 × BVDD of the signal
in question for 3.3-V signaling levels.
5. Input timings are measured at the pin.
6. The value of tLBOTOT is the measurement of the minimum time between the negation of LALE and any change in LAD.
7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
Table 43. Local Bus General Timing Parameters—PLL Bypassed (continued)
Parameter
Symbol1
Min
Max
Unit
Notes
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