參數(shù)資料
型號(hào): MPC8533EVTANGA
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 66/112頁(yè)
文件大?。?/td> 0K
描述: MPU POWERQUICC 783-PBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC85xx
處理器類(lèi)型: 32-位 MPC85xx PowerQUICC III
速度: 800MHz
電壓: 0.95 V ~ 1.05 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤(pán)
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
57
PCI
15.2
PCI AC Electrical Specifications
This section describes the general AC timing parameters of the PCI bus. Note that the SYSCLK signal is
used as the PCI input clock. Table 51 provides the PCI AC timing specifications at 66 MHz.
Figure 37 provides the AC test load for PCI.
Figure 37. PCI AC Test Load
Table 51. PCI AC Timing Specifications at 66 MHz
Parameter
Symbol1
Min
Max
Unit
Notes
SYSCLK to output valid
tPCKHOV
7.4
ns
2, 3
Output hold from SYSCLK
tPCKHOX
2.0
ns
2
SYSCLK to output high impedance
tPCKHOZ
—14
ns
2, 4
Input setup to SYSCLK
tPCIVKH
3.7
ns
2, 5
Input hold from SYSCLK
tPCIXKH
0.5
ns
2, 5
REQ64 to HRESET9 setup time
tPCRVRH
10
t
SYS
—clocks
6, 7
HRESET to REQ64 hold time
tPCRHRX
050
ns
7
HRESET high to first FRAME assertion
tPCRHFV
10
clocks
8
Rise time (20%–80%)
tPCICLK
0.6
2.1
ns
Fall time (20%–80%)
tPCICLK
0.6
2.1
ns
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing
(PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK clock, tSYS, reference (K)
going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R)
went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. All PCI signals are measured from OVDD/2 of the rising edge of PCI_SYNC_IN to 0.4 OVDD of the signal in question for
3.3-V PCI signaling levels.
4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
5. Input timings are measured at the pin.
6. The timing parameter tSYS indicates the minimum and maximum CLK cycle times for the various specified frequencies. The
system clock period must be kept within the minimum and maximum defined ranges. For values see Section 19, “Clocking.”
7. The setup and hold time is with respect to the rising edge of HRESET.
8. The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local Bus
Specifications.
9. The reset assertion timing requirement for HRESET is 100
s.
Output
Z0 = 1 K
OVDD/2
RL = 50
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MPC8533EVTARJA 功能描述:微處理器 - MPU PQ38K 8533E RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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