參數(shù)資料
型號: MPC8533EVTANGA
廠商: Freescale Semiconductor
文件頁數(shù): 78/112頁
文件大小: 0K
描述: MPU POWERQUICC 783-PBGA
標準包裝: 36
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 800MHz
電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
68
Freescale Semiconductor
PCI Express
17 PCI Express
This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8533E.
17.1
DC Requirements for PCI Express SD_REF_CLK and
SD_REF_CLK
17.2
AC Requirements for PCI Express SerDes Clocks
Table 53 provides the AC requirements for the PCI Express SerDes clocks.
17.3
Clocking Dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)
of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.
17.4
Physical Layer Specifications
The following is a summary of the specifications for the physical layer of PCI Express on this device. For
further details as well as the specifications of the transport and data link layer please refer to the
PCI Express Base Specification. Rev. 1.0a.
Table 53. SD_REF_CLK and SD_REF_CLK AC Requirements
Symbol2
Parameter Description
Min
Typ
Max
Units
Notes
tREF
REFCLK cycle time
10
ns
1
tREFCJ
REFCLK cycle-to-cycle jitter. Difference in the period of any
two adjacent REFCLK cycles
——
100
ps
tREFPJ
Phase jitter. Deviation in edge location with respect to
mean edge location
–50
50
ps
Notes:
1. Typical based on PCI Express Specification 2.0.
2. Guaranteed by characterization.
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