參數(shù)資料
型號(hào): MPC8547ECPXAQGB
廠商: Freescale Semiconductor
文件頁數(shù): 140/151頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 783-PBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor
89
Serial RapidIO
18.8
Receiver Eye Diagrams
For each baud rate at which an LP-serial receiver is specified to operate, the receiver shall meet the
corresponding bit error rate specification (Table 66, Table 67, and Table 68) when the eye pattern of the
receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the receiver
input compliance mask shown in Figure 54 with the parameters specified in Table 69. The eye pattern of
the receiver test signal is measured at the input pins of the receiving device with the device replaced with
a 100-
± 5% differential resistive load.
Figure 54. Receiver Input Compliance Mask
18.9
Measurement and Test Requirements
Since the LP-serial electrical specification are guided by the XAUI electrical interface specified in
Clause 47 of IEEE Std. 802.3ae-2002, the measurement and test requirements defined here are similarly
guided by Clause 47. Additionally, the CJPAT test pattern defined in Annex 48A of IEEE Std.
Table 69. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter
Receiver Type
VDIFFmin
(mV)
VDIFFmax
(mV)
A (UI)
B (UI)
1.25 GBaud
100
800
0.275
0.400
2.5 GBaud
100
800
0.275
0.400
3.125 GBaud
100
800
0.275
0.400
1
0
VDIFF max
–VDIFF max
VDIFF min
–VDIFF min
Time (UI)
Recei
v
e
r
Di
ff
e
re
n
tial
Inpu
tV
o
lt
age
0
AB
1-B
1-A
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