參數(shù)資料
型號: MPC8547ECPXAQGB
廠商: Freescale Semiconductor
文件頁數(shù): 35/151頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 783-PBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor
13
Electrical Characteristics
2.1.3
Output Driver Characteristics
The following table provides information on the characteristics of the output driver strengths. The values
are preliminary estimates.
2.2
Power Sequencing
The device requires its power rails to be applied in a specific sequence in order to ensure proper device
operation. These requirements are as follows for power-up:
1. VDD, AVDD_n, BVDD, LVDD, OVDD, SVDD, TVDD, XVDD
2. GVDD
All supplies must be at their stable values within 50 ms.
NOTE
Items on the same line have no ordering requirement with respect to one
another. Items on separate lines must be ordered sequentially such that
voltage rails on a previous step must reach 90% of their value before the
voltage rails on the current step reach 10% of theirs.
NOTE
In order to guarantee MCKE low during power-up, the above sequencing for
GVDD is required. If there is no concern about any of the DDR signals being
in an indeterminate state during power-up, then the sequencing for GVDD is
not required.
Table 3. Output Drive Capability
Driver Type
Programmable
Output Impedance
(
)
Supply
Voltage
Notes
Local bus interface utilities signals
25
BVDD = 3.3 V
BVDD = 2.5 V
45(default)
BVDD = 3.3 V
BVDD = 2.5 V
PCI signals
25
OVDD = 3.3 V
45(default)
DDR signal
18
36 (half strength mode)
GVDD = 2.5 V
DDR2 signal
18
36 (half strength mode)
GVDD = 1.8 V
TSEC/10/100 signals
45
L/TVDD = 2.5/3.3 V
DUART, system control, JTAG
45
OVDD = 3.3 V
I2C
150
OVDD = 3.3 V
Notes:
1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR.
2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT1 signal at reset.
3. The drive strength of the DDR interface in half-strength mode is at Tj = 105C and at GVDD (min).
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