參數(shù)資料
型號: MPC8555VTAPF
廠商: Freescale Semiconductor
文件頁數(shù): 10/88頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC III 783-FCPBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 833MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
配用: CWH-PPC-8540N-VE-ND - KIT EVAL SYSTEM MPC8540
MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 4.2
18
Freescale Semiconductor
DDR SDRAM
6.2
DDR SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1
DDR SDRAM Input AC Timing Specifications
Table 13 provides the input AC timing specifications for the DDR SDRAM interface.
6.2.2
DDR SDRAM Output AC Timing Specifications
Table 14 and Table 15 provide the output AC timing specifications and measurement conditions for the
DDR SDRAM interface.
Table 13. DDR SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of 2.5 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
VIL
—MVREF – 0.31
V
AC input high voltage
VIH
MVREF + 0.31
GVDD + 0.3
V
MDQS—MDQ/MECC input skew per
byte
For DDR = 333 MHz
For DDR < 266 MHz
tDISKEW
750
1125
ps
1
Note:
1. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0 <= n <=
7) or ECC (MECC[{0...7}] if n = 8).
Table 14. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode
At recommended operating conditions with GVDD of 2.5 V ± 5%.
Parameter
Symbol 1
Min
Max
Unit
Notes
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
tMCK
610
ns
2
Skew between any MCK to ADDR/CMD
333 MHz
266 MHz
200 MHz
tAOSKEW
–1000
–1100
–1200
200
300
400
ps
3
ADDR/CMD output setup with respect to MCK
333 MHz
266 MHz
200 MHz
tDDKHAS
2.8
3.45
4.6
—ns
4
ADDR/CMD output hold with respect to MCK
333 MHz
266 MHz
200 MHz
tDDKHAX
2.0
2.65
3.8
—ns
4
MCS(n) output setup with respect to MCK
333 MHz
266 MHz
200 MHz
tDDKHCS
2.8
3.45
4.6
—ns
4
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