參數(shù)資料
型號(hào)： MPC8555VTAPF
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 39/88頁(yè)
文件大?。?/td> 0K
描述： IC MPU POWERQUICC III 783-FCPBGA
標(biāo)準(zhǔn)包裝： 36
系列： MPC85xx
處理器類(lèi)型： 32-位 MPC85xx PowerQUICC III
速度： 833MHz
電壓： 1.2V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤(pán)
配用： CWH-PPC-8540N-VE-ND - KIT EVAL SYSTEM MPC8540
MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 4.2
44
Freescale Semiconductor
CPM
Figure 23 provides the AC test load for the CPM.
Figure 23. CPM AC Test Load
TDM inputs/SI—hold time
tTDIXKH
3ns
PIO inputs—input setup time
tPIIVKH
8ns
PIO inputs—input hold time
tPIIXKH
1ns
COL width high (FCC)
tFCCH
1.5
CLK
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings
are measured at the pin.
2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFIIVKH
symbolizes the FCC inputs internal timing (FI) with respect to the time the input signals (I) reaching the valid state (V)
relative to the reference clock tFCC (K) going to the high (H) state or setup time. And tTDIXKH symbolizes the TDM timing
(TD) with respect to the time the input signals (I) reach the invalid state (X) relative to the reference clock tFCC (K) going to
the high (H) state or hold time.
3. PIO and TIMER inputs and outputs are asynchronous to SYSCLK or any other externally visible clock. PIO/TIMER inputs
are internally synchronized to the CPM internal clock. PIO/TIMER outputs should be treated as asynchronous.
Table 34. CPM Output AC Timing Specifications 1
Characteristic
Symbol 2
Min
Max
Unit
FCC outputs—internal clock (NMSI) delay
tFIKHOX
15.5
ns
FCC outputs—external clock (NMSI) delay
tFEKHOX
28
ns
SCC/SMC/SPI outputs—internal clock (NMSI) delay
tNIKHOX
0.5
10
ns
SCC/SMC/SPI outputs—external clock (NMSI) delay
tNEKHOX
28
ns
TDM outputs/SI delay
tTDKHOX
2.5
11
ns
PIO outputs delay
tPIKHOX
111
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFIKHOX symbolizes the FCC
inputs internal timing (FI) for the time tFCC memory clock reference (K) goes from the high state (H) until outputs (O) are
invalid (X).
Table 33. CPM Input AC Timing Specifications 1 (continued)
Characteristic
Symbol 2
Min3
Unit
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
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