參數(shù)資料
型號(hào): MPC8555VTAPF
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 18/88頁(yè)
文件大?。?/td> 0K
描述: IC MPU POWERQUICC III 783-FCPBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC85xx
處理器類(lèi)型: 32-位 MPC85xx PowerQUICC III
速度: 833MHz
電壓: 1.2V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤(pán)
配用: CWH-PPC-8540N-VE-ND - KIT EVAL SYSTEM MPC8540
MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
25
Ethernet: Three-Speed, MII Management
8.2.2.1
GMII Receive AC Timing Specifications
Table 21 provides the GMII receive AC timing specifications.
Figure 8 provides the AC test load for TSEC.
Figure 8. TSEC AC Test Load
Figure 9 shows the GMII receive AC timing diagram.
Figure 9. GMII Receive AC Timing Diagram
Table 21. GMII Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
RX_CLK clock period
tGRX
—8.0
ns
RX_CLK duty cycle
tGRXH/tGRX
40
60
%
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
tGRDVKH
2.0
ns
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
tGRDXKH
0.5
ns
RX_CLK clock rise and fall time
tGRXR, tGRXF
2,3
——
1.0
ns
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH
symbolizes GMII receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to
the tRX clock reference (K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR)
with respect to the time data input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L)
state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing
the clock of a particular functional. For example, the subscript of tGRX represents the GMII (G) receive (RX) clock. For rise
and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3. Guaranteed by design.
Output
Z0 = 50 Ω
LVDD/2
RL = 50 Ω
RX_CLK
RXD[7:0]
tGRDXKH
tGRX
tGRXH
tGRXR
tGRXF
tGRDVKH
RX_DV
RX_ER
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