參數(shù)資料
型號： MPC8569VTANKGB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783
文件頁數(shù)： 120/126頁
文件大小： 2847K
代理商： MPC8569VTANKGB
Serial RapidIO (SRIO)
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
93
2.11.4.2
AC Requirements for Serial RapidIO Transmitter
The following table defines the transmitter AC specifications for the Serial RapidIO. The AC timing specifications do not
include RefClk jitter
The following table defines the receiver AC specifications for Serial RapidIO. The AC timing specifications do not include
RefClk jitter.
Table 54. SRIO Transmitter AC Timing Specifications
At recommended operating conditions with XVDD = 1.0 V ± 3%. and 1.1 V ± 3%
Parameter
Symbol
Min
Typical
Max
Unit
Notes
Deterministic jitter
JD
—
0.17
UI p-p
—
Total jitter
JT
—
0.35
UI p-p
—
Unit Interval: 1.25 GBaud
UI
800 – 100ppm
800
800 + 100ppm
ps
—
Unit Interval: 2.5 GBaud
UI
400 – 100ppm
400
400 + 100ppm
ps
—
Unit Interval: 3.125 GBaud
UI
320 – 100ppm
320
320 + 100ppm
ps
—
Table 55. SRIO Receiver AC Timing Specifications
At recommended operating conditions with ScoreVDD = 1.0 V ± 3%. and 1.1 V ± 3%.
Parameter
Symbol
Min
Typical
Max
Unit
Notes
Deterministic jitter tolerance
JD
0.37
—
UI p-p
1, 3
Combined deterministic and random jitter
tolerance
JDR
0.55
—
UI p-p
1, 3
Total jitter tolerance2
JT
0.65
—
UI p-p
1, 3
Bit error rate
BER
—
10–12
——
Unit Interval: 1.25 GBaud
UI
800 – 100ppm
800
800 + 100ppm
ps
—
Unit Interval: 2.5 GBaud
UI
400 – 100ppm
400
400 + 100ppm
ps
—
Unit Interval: 3.125 GBaud
UI
320 – 100ppm
320
320 + 100ppm
ps
—
Notes:
1. Measured at receiver
2. Total jitter is composed of three components: deterministic jitter, random jitter and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 48. The sinusoidal jitter component
is included to ensure margin for low-frequency jitter, wander, noise, crosstalk, and other variable system effects.
3. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing
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