參數(shù)資料
型號: MPC8569VTANKGB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783
文件頁數(shù): 60/126頁
文件大?。?/td> 2847K
代理商: MPC8569VTANKGB
Overall DC Electrical Characteristics
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
39
The following figure shows the undershoot and overshoot voltages at the interfaces of the MPC8569E.
Figure 7. Overshoot/Undershoot Voltage for BVDD/GVDD/LVDD/OVDD/XVDD
The core voltage must always be provided at nominal 1.0 or 1.1 V. See Table 3 for actual recommended core voltage. Voltage
to the processor interface I/Os is provided through separate sets of supply pins and must be provided at the voltages shown in
Table 3. The input voltage threshold scales with respect to the associated I/O supply voltage. (B,M,L,O)VDD based receivers
are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR2 and DDR3 SDRAM interface
uses differential receivers referenced by the externally supplied Dn_MVREF signal (nominally set to GVDD/2) as is appropriate
for the SSTL_1.8 electrical signaling standard for DDR2 or 1.5-V electrical signaling for DDR3. The DDR DQS receivers
cannot be operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded.
GND
GND – 0.3 V
GND – 0.7 V
Not to Exceed 10%
Nominal (B,G,L,O,X)VDD + 20%
(B,G,L,O,X)VDD
(B,G,L,O,X)VDD + 5%
of tCLOCK
1
1. Note that tCLOCK refers to the clock period associated with the respective interface:
VIH
VIL
Note:
For DDR, tCLOCK references Dn_MCK.
For eLBC, tCLOCK references LCLKn
For I2C and JTAG, tCLOCK references SYSCLK.
.For eLBC, tCLOCK references LCLKn
For SerDEs XVDD, tCLOCK references SD_REF_CLK.
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