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參數(shù)資料
| 型號： | MPC9330ACR2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLOCK GENERATOR 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | PLL 時鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，晶體 |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:6 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 120MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
DATA SHEET
MPC9330 REVISION 8 DECEMBER 19, 2012
1
2012 Integrated Device Technology, Inc.
3.3V, 1:6, LVCMOS PLL Clock Generator
MPC9330
NRND
The MPC9330 is a 3.3 V compatible, 1:6 PLL based clock generator targeted for high
performance low-skew clock distribution in mid-range to high-performance telecomm,
networking and computing applications. With output frequencies up to 120 MHz and output
skews less than 150 ps, the device meets the needs of the most demanding clock applications.
The MPC9330 is specified for the temperature range of 0°C to +70°C.
Features
1:6 PLL Based Low-Voltage Clock Generator
3.3 V Power Supply
Generates Clock Signals Up to 120 MHz
Maximum Output Skew of 150 ps
On-Chip Crystal Oscillator Clock Reference
Alternative LVCMOS PLL Reference Clock Input
Internal and External PLL Feedback
PLL Multiplies the Reference Clock by 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x,
x/2, x/3, or x/4
Supports Zero-Delay Operation in External Feedback Mode
Synchronous Output Clock Stop in Logic Low Eliminates Output Runt Pulses
Power_Down Feature Reduces Output Clock Frequency
Drives Up to 12 Clock Lines
32-Lead LQFP Packaging
32-Lead Pb-Free Package
Ambient Temperature Range 0
C to +70C
Internal Power-Up Reset
Pin and Function Compatible to the MPC930
Functional Description
The MPC9330 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9330
requires either the selection of internal PLL feedback or the connection of one of the device outputs to the feedback input to close the PLL
feedback path in external feedback mode. The reference clock frequency and the divider for the feedback path determine the VCO frequency.
Both must be selected to match the VCO frequency range. In external PLL feedback configuration and with the available post-PLL dividers
(divide-by-2, divide-by-4 and divide-by-6), the internal VCO of the MPC9330 is running at either 4x, 8x, 12x, 16x, or 24x of the reference clock
frequency. In internal feedback configuration (divide-by-16) the internal VCO is running 16x of the reference frequency. The frequency of the
QA, QB, QC output banks is a division of the VCO frequency and can be configured independently for each output bank using the FSELA,
FSELB and FSELC pins, respectively. The available output to input frequency ratios are 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3, or x/4.
The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible input as the reference clock signal. The PLL_EN control
selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the
output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL
characteristics do not apply.
The outputs can be disabled (high-impedance) by deasserting the OE/MR pin. In the PLL configuration with external feedback selected,
deasserting OE/MR causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Asserting OE/MR will enable the outputs
and close the phase locked loop, enabling the PLL to recover to normal operation. The MPC9330 output clock stop control allows the outputs
to start and stop synchronously in the logic low state, without the potential generation of runt pulses.
The MPC9330 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except XTAL) accept LVCMOS signals
while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50
transmission lines. For series terminated
transmission lines, each of the MPC9330 outputs can drive one or two traces giving the devices an effective fanout of 1:12. The device is
packaged in a 7x7 mm2 32-lead LQFP package.
MPC9330
3.3 V 1:6 LVCMOS
PLL CLOCK GENERATOR
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
NRND – Not Recommend for New Designs
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9330FA | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3.3V 200MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9330FAR2 | 制造商:Integrated Device Technology Inc 功能描述:MPC9330FAR2 - Tape and Reel |
| MPC9331 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3 V 1:6 LVCMOS PLL Clock Generator |
| MPC9331AC | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL1-6 LVCMOS/LVPECL LVCMOS PLL Clk Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9331ACR2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL1-6 LVCMOS/LVPECL LVCMOS PLL Clk Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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