參數(shù)資料
型號(hào): MPC9330ACR2
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 13/13頁
文件大?。?/td> 0K
描述: IC PLL CLOCK GENERATOR 32-LQFP
標(biāo)準(zhǔn)包裝: 2,000
類型: PLL 時(shí)鐘發(fā)生器
PLL: 帶旁路
輸入: LVCMOS,晶體
輸出: LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 3:6
差分 - 輸入:輸出: 無/無
頻率 - 最大: 120MHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 32-LQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
包裝: 帶卷 (TR)
MPC9330 REVISION 8 DECEMBER 19, 2012
9
2012 Integrated Device Technology, Inc.
MPC9330 Data Sheet
3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR
VL =VS ( Z0 (RS+R0 + Z0))
Z0 = 50 || 50
RS = 36 || 36
R0 = 14
VL = 3.0 (25 (18+14+25)
= 1.31 V
At the load end, the voltage will double due to the near unity
reflection coefficient, to 2.6 V. It will then increment towards the
quiescent 3.0 V in steps separated by one round trip delay (in this
case 4.0 ns).
Final skew data pending specification.
Figure 5. Single versus Dual Waveforms
Since this step is well above the threshold region, it will not cause
any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better match
the impedances when driving multiple lines, the situation in Figure 6
should be used. In this case the series terminating resistors are
reduced such that when the parallel combination is added to the
output buffer impedance, the line impedance is perfectly matched.
Figure 6. Optimized Dual Line Termination
Figure 7. CCLK MPC9330 AC Test Reference for Vcc = 3.3 V
Time (ns)
Vo
ltag
e(V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
tD = 3.9386
OutA
tD = 3.8956
In
14
+ 22 || 22 = 50 || 50
25
= 25
14
MPC9330
Output
Buffer
RS = 22
ZO = 50
RS = 22
ZO = 50
Pulse
Generator
Z = 50
RT = 50
ZO = 50
RT = 50
ZO = 50
MPC9930 DUT
VTT
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