參數(shù)資料
型號: MPC9330ACR2
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 9/13頁
文件大?。?/td> 0K
描述: IC PLL CLOCK GENERATOR 32-LQFP
標(biāo)準(zhǔn)包裝: 2,000
類型: PLL 時鐘發(fā)生器
PLL: 帶旁路
輸入: LVCMOS,晶體
輸出: LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 3:6
差分 - 輸入:輸出: 無/無
頻率 - 最大: 120MHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 32-LQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
包裝: 帶卷 (TR)
MPC9330 REVISION 8 DECEMBER 19, 2012
5
2012 Integrated Device Technology, Inc.
MPC9330 Data Sheet
3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR
Table 7. AC Characteristics (VCC = 3.3 V 5%, TA = 0°C to 70°C)(1)
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Reference Frequency(2)
4 feedback(3)
PLL mode, external feedback
8 feedback
12 feedback
16 feedback
24 feedback
PLL mode, internal feedback
16 feedback)
Input Reference Frequency in PLL bypass mode(4)
2. PLL mode requires PLL_EN = 0 to enable the PLL.
3.
4 feedback (FB) can be accomplished by setting PWR_DN = 0 and the connection of one 2 output to FB_IN. See Table 3 to Table 5 for
other feedback configurations.
4. In bypass mode, the MPC9330 divides the input reference clock.
50
25
16.67
12.5
8.33
12.5
120
60
40
30
20
30
TBD
MHz
PLL locked
fVCO
VCO Lock Frequency Range(5)
5. The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO FB.
200
480
MHz
fXTAL
Crystal Interface Frequency Range(6)
6. The usable crystal frequency range depends on the VCO lock frequency and the PLL feedback ratio.
10
25
MHz
fMAX
Output Frequency
4 output
8 output
12 output
16 output
24 output
50
25
16.67
12.5
8.33
120
60
40
30
20
MHz
PLL locked
frefDC
tPW, MIN
Reference Input Duty Cycle
Minimum Input Reference Pulse Width
25
2
75
%
ns
tr, tf
CCLK Input Rise/Fall Time
1.0
ns
0.8 to 2.0 V
t()
Propagation Delay (SPO)(7) for the
- entire fref range
- fref = 8.33 MHz
- fref = 50.0 MHz
7. SPO is the static phase offset between CCLK and FB_IN (FB_SEL=1 and PLL locked). tsk(o) [ps] = tsk(o) [°] B(fref 360°)
-1.2
-400
-70
+1.2
+400
+70
°
ps
tsk(o)
Output-to-Output Skew(8)
(within output bank)
(any output)
8. Skew data applicable for equally loaded outputs only.
50
150
ps
DC
Output Duty Cycle
45
50
55
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4 V
tPLZ, HZ
Output Disable Time
10
ns
tPZL, LZ
Output Enable Time
10
ns
tJIT(CC)
Cycle-to-cycle jitter
50
300
ps
tJIT(PER)
Period Jitter
35
250
ps
tJIT()
I/O Phase Jitter
RMS (1
)
10
70
ps
BW
PLL closed loop bandwidth(9)
4 feedback
PLL mode, external feedback
8 feedback
12 feedback
16 feedback
24 feedback
9. –3 dB point of PLL transfer characteristics.
0.8-5.0
0.5-2.0
0.3-1.0
0.25-0.6
0.2-0.5
MHz
tLOCK
Maximum PLL Lock Time
10
ms
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