參數(shù)資料
型號: MPC9330ACR2
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 2/13頁
文件大?。?/td> 0K
描述: IC PLL CLOCK GENERATOR 32-LQFP
標準包裝: 2,000
類型: PLL 時鐘發(fā)生器
PLL: 帶旁路
輸入: LVCMOS,晶體
輸出: LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 3:6
差分 - 輸入:輸出: 無/無
頻率 - 最大: 120MHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 32-LQFP
供應商設備封裝: 32-TQFP(7x7)
包裝: 帶卷 (TR)
MPC9330 REVISION 8 DECEMBER 19, 2012
10
2012 Integrated Device Technology, Inc.
MPC9330 Data Sheet
3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR
Figure 8. Output-to-Output Skew tSK(O)
Figure 9. Propagation Delay (t(), static phase offset)
Test Reference
Figure 10. Output Duty Cycle (DC)
Figure 11. I/O Jitter
TJIT() = |T0–T1mean|
CCLK
FB_EN
The deviation in t0 for a controlled edge with respect to a t0 mean
in a random sample of cycles
VCC
VCC 2
GND
VCC
VCC 2
GND
t()
CCLK
FB_IN
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device
VCC
VCC 2
GND
VCC
VCC 2
GND
tSK(O)
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
VCC
VCC 2
GND
tP
T0
DC = tP/T0 x 100%
Figure 12. Cycle-to-Cycle Jitter
Figure 13. Period Jitter
Figure 14. Output Transition Time Test Reference
tF
tR
VCC=3.3 V
2.4
0.55
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
TN
TJIT(CC) = |TN–TN+1|
TN+1
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles
TJIT(PER) = |TN–1/f0|
T0
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