參數(shù)資料
型號: MPC96877EP
廠商: MOTOROLA INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40
封裝: 6 X 6 MM, 0.50 MM PITCH, LEAD FREE, MO-220VJJD-2, MLF-40
文件頁數(shù): 12/16頁
文件大?。?/td> 221K
代理商: MPC96877EP
MPC96877
TIMING SOLUTIONS
5
MOTOROLA
Table 3. Absolute Maximum Ratings over Free-Air Operating Range1
1.
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Parameter
Value
Supply voltage range, VDDQ or AVDD
–0.5 V to 2.5 V
Input voltage range, VI
2 3
2.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3.
This value is limited to 2.5 V maximum.
–0.5 V to VDDQ + 0.5 V
Output voltage range, VO
1 2
–0.5 V to VDDQ + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VDDQ)
±50 mA
Output clamp voltage, IOK (VO < 0 or VO > VDDQ)
±50 mA
Continuous output current, IO (VO = 0 to VDDQ)
±50 mA
Continuous current through each VDDQ or GND
±100 mA
Storage temperature range, TSTG
–65
°C to 150°C
Table 4. Recommended Operating Conditions
Rating
Parameter
Affected Pins
Min
Nom
Max
Unit
Output supply voltage
VDDQ
1.7
1.8
1.9
V
Supply voltage1
1.
The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the recommended
operating conditions and not timing parameters are guaranteed.
AVDD
VDDQ
Low-level input voltage2
2.
VID is the magnitude of the difference between the input level on CK and the input level on CK, see Figure 12 for definition. For CK and CK the
VIH and VIL limits are used to define the DC low and high levels for the logic detect state.
VIL
OE, OS,CK, CK
0.35 x VDDQ
V
High-level input voltage2
VIH
OE, OS,CK, CK
0.65 x VDDQ
High-level output current
IOH
–9
mA
Low-level output current
IOL
9
mA
Input differential-pair cross voltage
VIX
(VDDQ/2)–0.15
(VDDQ/2)+0.15
V
Input voltage level
VIN
–0.3
VDDQ +0.3
Input differential-pair voltage2
(see Figure 9)
VID
DC
0.3
VDDQ +0.4
AC
0.6
VDDQ +0.4
Operating free-air temperature
0
70
°C
相關(guān)PDF資料
PDF描述
MPC97R73FA PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
MPC9892FA PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC9991FA PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
MQ80C154-16P883R 8-BIT, 16 MHz, MICROCONTROLLER, CQFP44
952100202 8-BIT, 30 MHz, MICROCONTROLLER, CQCC44
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC96877VK 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 DDR2 PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
MPC96877VKR2 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 DDR2 PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
MPC970 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER
MPC972 制造商:Motorola Inc 功能描述:
MPC972FA 制造商:Freescale Semiconductor 功能描述: