2–64
Motorola Sensor Device Data
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Figure 4. Aliasing Comparison
(a)
(b)
(c)
SAMPLING
FREQUENCY
INJECTED SIGNAL
FREQUENCY
1.0E+0
1.0E–1
1.0E–3
1.0E–2
1.0E–4
1.0E–5
1.0E–6
41.0
41.2
41.4
FREQUENCY (kHz)
41.6
41.8
42.0
V
Vout
1.0E+0
1.0E–1
1.0E–3
1.0E–2
1.0E–4
1.0E–5
1.0E–6
1.0E–7
41.0
41.2
41.4
FREQUENCY (kHz)
41.6
41.8
42.0
V
VCC
SAMPLING
FREQUENCY
INJECTED SIGNAL
FREQUENCY
1.0E+0
1.0E–1
1.0E–3
1.0E–2
1.0E–4
1.0E–5
1.0E–60
200
400
FREQUENCY (Hz)
600
800
1000
V
Vout
Points to note:
Under clean dc bias, Vout and VCC, Figures 3a and 3b have
a signal component at the sampling rate. This is due to
switched capacitor currents coupling through finite power
supply source impedances and PCB paracitics.
The low frequency output spectrum, Figure 3c, displays the
internal lowpass filter characteristics. (The filter and sam-
pling characteristics are sometimes useful in system de-
bugging.)
When an ac component is superimposed onto VCC near
the sampling frequency, as shown in Figure 4b, the output
will contain the original signal plus a mirrored signal about
the sampling frequency, shown in Figure 4a. Signals on the
VCC line will appear at the output due to the ratiometric
characteristic of the accelerometer and will be one half the
amplitude.
As a result of sampling, the output waveform of Figure 4c
is produced where the injected high frequency signal has
now produced a signal in the passband.
Harmonics of the aliased signal in the pass band are also
shown in Figure 4c.
Aliased signals in the passband will be amplified versions
of the injected signals. This is due to the signal conditioning
circuitry in the accelerometer that includes gain.
ALIASING AVOIDANCE KEYS
Use a linear regulated power source when feasible. Linear
regulators have excellent power supply rejection offering a
stable dc source.
If using a switching power supply, ensure that the switching
frequency is not close to the accelerometer sampling fre-
quency or its harmonics. Noting that the accelerometer will
gain the aliasing signal, it is desirable to keep frequencies
at least 4 kHz away from the sampling frequency and its
harmonics. 4 kHz is one decade from the –3 dB frequency,
therefore any signals will be sufficiently attenuated by the
internal 4–pole lowpass filter.
Proper bias decoupling will aid in noise reduction from oth-
er sources. With dense surface mount PCB assemblies, it
is often difficult to place and route decoupling components.
However, the accelerometer is not like a typical logic de-
vice. A little extra effort on decoupling goes a long way.
Good PCB layout practices should always be followed.
Proper system grounding is essential. Parasitic capaci-
tance and inductance could prove to be troublesome, par-
ticularly during EMC testing. Signal harmonics and
sub–harmonics play a significant role in introducing aliased
signals. Clean layouts minimize the effects of parasitics
and thus signal harmonics and sub–harmonics.
F
Freescale Semiconductor, Inc.
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