2–57
Motorola Sensor Device Data
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OPERATING CHARACTERISTICS
(Unless otherwise noted: –40
°
C
TA
+85
°
C, 4.75
VDD
5.25, X and Y Channels, Acceleration = 0g, Loaded output(1))
Characteristic
Symbol
Min
Typ
Max
Unit
Operating Range(2)
Supply Voltage(3)
Supply Current
Operating Temperature Range
Acceleration Range
VDD
IDD
TA
gFS
4.75
6
40
—
5.00
8
—
45
5.25
10
+85
—
V
mA
°
C
g
Output Signal
Zero g (VDD = 5.0 V)(4)
Zero g
Sensitivity (TA = 25
°
C, VDD = 5.0 V)(5)
Sensitivity
Bandwidth Response
Nonlinearity
VOFF
VOFF,V
S
SV
f–3dB
NLOUT
2.2
0.44 VDD
45
9
360
1.0
2.5
0.50 VDD
50
10
400
—
2.8
0.56 VDD
55
11
440
+1.0
V
V
mV/g
mV/g/V
Hz
% FSO
Noise
RMS (.01–1 kHz)
Power Spectral Density
Clock Noise (without RC load on output)(6)
nRMS
nPSD
nCLK
—
—
—
—
110
2.0
2.8
—
—
mVrms
μ
V/(Hz1/2)
mVpk
Self–Test
Output Response
Input Low
Input High
Input Loading(7)
Response Time(8)
Status(12)(13)
Output Low (Iload = 100
μ
A)
Output High (Iload = 100
μ
A)
gST
VIL
VIH
IIN
tST
9.6
VSS
0.7 x VDD
30
—
12
—
—
110
2.0
14.4
0.3 x VDD
VDD
300
—
g
V
V
μ
A
ms
VOL
VOH
—
VDD
.8
—
—
0.4
—
V
V
Minimum Supply Voltage (LVD Trip)
VLVD
fmin
2.7
3.25
4.0
V
Clock Monitor Fail Detection Frequency
50
—
260
kHz
Output Stage Performance
Electrical Saturation Recovery Time(9)
Full Scale Output Range (IOUT = 200
μ
A)
Capacitive Load Drive(10)
Output Impedance
tDELAY
VFSO
CL
ZO
—
0.3
—
—
0.2
—
—
300
—
VDD
0.3
100
—
ms
V
pF
Mechanical Characteristics
Transverse Sensitivity(11)
Package Resonance
VZX,YX
fPKG
—
—
—
10
5.0
—
% FSO
kHz
NOTES:
1. For a loaded output the measurements are observed after an RC filter consisting of a 1 k
resistor and a 0.01
μ
F capacitor to ground.
2. These limits define the range of operation for which the part will meet specification.
3. Within the supply range of 4.75 and 5.25 volts, the device operates as a fully calibrated linear accelerometer. Beyond these supply limits
the device may operate as a linear device but is not guaranteed to be in calibration.
4. The device can measure both + and acceleration. With no input acceleration the output is at midsupply. For positive acceleration the output
will increase above VDD/2 and for negative acceleration the output will decrease below VDD/2.
5. The device is calibrated at 20g.
6. At clock frequency
70 kHz.
7. The digital input pin has an internal pull–down current source to prevent inadvertent self test initiation due to external board level leakages.
8. Time for the output to reach 90% of its final value after a self–test is initiated.
9. Time for amplifiers to recover after an acceleration signal causing them to saturate.
10. Preserves phase margin (60
°
) to guarantee output amplifier stability.
11. A measure of the device’s ability to reject an acceleration applied 90
°
from the true axis of sensitivity.
12. The Status pin output is not valid following power–up until at least one rising edge has been applied to the self–test pin. The Status pin is
high whenever the self–test input is high.
13. The Status pin output latches high if a Low Voltage Detection or Clock Frequency failure occurs, or the EPROM parity changes to odd. The
Status pin can be reset by a rising edge on self–test, unless a fault condition continues to exist.
F
Freescale Semiconductor, Inc.
n
.