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Motorola Sensor Device Data
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microcontroller’s output compare pin. The equation is similar
to the one above for Current Pressure:
High Time @ Full–Scale Pressure – High Time @
Zero Pressure
Full–Scale Pressure in kPa
Current High Time – High Time @ Zero Pressure
Current Pressure =
Via this equation, the digital nature of the design is revealed.
The analog voltage signal has been translated into a signal in
the time domain where the high time generated by the output
compare pin is actually the digital time representation of the
sensor’s output. Since the user precisely controls the high
time of the pulse train (and period) via software which is based
on the accurate digital time base of the microcontroller, the
digital representation of the signal is very stable and accurate.
Additionally, the high accuracy of the digital representation is
possible since all the user must do to digitize the signal is
detect a single logic–level transition at the comparator’s
output.
SYSTEM DESIGN: DEFINING AND DESIGNING
FOR A DESIRED SIGNAL RESOLUTION
The resolution is directly related to the period (and thus
frequency) of the pulse train. In our design, the difference
between the pulse train’s high time at full scale pressure and
the pulse train’s high time and zero pressure must be 512
μ
s
to obtain at least 8–bit resolution. This is determined by the
fact that a 4 MHz crystal yields a 2 MHz clock speed in the
MC68HC05P9 microcontroller. This, in turn, translates to
0.5
μ
s per clock tick. There are four clock cycles per timer
count. This results in 2
μ
s per timer count. Thus, to obtain 256
timer counts (discrete high–time time intervals or 8–bit
resolution), the difference between the zero pressure and full
scale pressure high times must be at least 2
μ
s x 256 = 512
μ
s.
To determine the pulse train’s maximum frequency (or
minimum period), the sensor’s analog dynamic range (span)
must be known. For this design, the span is 4 V. Thus the 4 V
span of the sensor must translate to 512
μ
s of time for 8–bit
resolution. But the pulse train typically has a logic–level high
value of 5 V, indicating that for a 100% duty cycle or a period
with all high time, the integrator’s output would be 5 V; likewise
for a duty cycle of 0% or a period with no high time, the output
would be 0 V. Therefore 512
μ
s accounts for only 4 V/5 V
(80%) of the pulse train’s total period. See Figure 2. . To
calculate the pulse train’s total period, divide the 512
μ
s by 4/5
(0.8) to obtain the required minimum period for the pulse train
of 640
μ
s. The reciprocal of this minimum period is the
maximum frequency (1.56 kHz) of the pulse train to obtain at
least 8–bit resolution.
To summarize:
The MC68HC05P9 runs off a 4 MHz crystal. The
microcontroller internally divides this frequency by two to yield
an internal clock speed of 2 MHz.
1
2 MHz
0.5
s
clock cycle
And,
4 clock cycles = 1 timer count.
Therefore,
4 clock cycles
timer count
For 8–bit resolution,
0.5
s
clock cycle
2
s
timer count
2
s
timer count
256 timer counts = 512
μ
s
which is the required minimum time into which the sensor’s
4 V span is translated.
To calculate the required period of the pulse train to yield the
0 to 5 V output (from 0% to 100% duty cycle based on the pulse
train’s logic–level high value of 5 V):
Minimum Required Period =
512
s for a 4 V sensor span
4 5 of integrator s output
Translating this to frequency, the maximum pulse train
frequency is thus
1
640
s
The above procedure can be implemented easily for other
resolution requirements (i.e. a resolution of 1%, 2%, etc.).
640
s
1.56 kHz.
Figure 2. Designing the Pulse Train’s Period for 8–Bit Resolution
5 V (PULSE TRAINS LOGIC–LEVEL ONE VALUE)
4.5 V (SENSOR’S ANALOG VOLTAGE OUTPUT
AT FULL–SCALE PRESSURE)
0.5 V (SENSOR’S ANALOG VOLTAGE OUTPUT
AT ZERO PRESSURE)
0 V (PULSE TRAINS LOGIC–LEVEL ZERO VALUE)
4.0 V SPAN
PULSE TRAIN HIGH TIME OF 640 s
(100% DUTY CYCLE)
PULSE TRAIN HIGH TIME OF 576 s
PULSE TRAIN HIGH TIME OF 64 s
512 s FOR 8–BIT RESOLUTION
PULSE TRAIN HIGH TIME OF 0 s
(0% DUTY CYCLE)
F
Freescale Semiconductor, Inc.
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