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參數(shù)資料
| 型號： | MQ80C52CXXX-20/883R |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁數(shù)： | 99/101頁 |
| 文件大?。?/td> | 3398K |
| 代理商： | MQ80C52CXXX-20/883R |
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120
8168C-MCU Wireless-02/10
AT86RF212
7.7.5 Clock Jitter
AT86RF212 provides receiver sensitivities up to -110 dBm. Detection of such small RF
signals requires very clean scenarios with respect to noise and interference. Harmonics
of digital signals may degrade the performance if they interfere with the wanted RF
signal. A small clock jitter of digital signals can spread harmonics over a wider
frequency range, thus reducing the power of certain spectral lines. AT86RF212
provides such a clock jitter as an optional feature. The jitter module is working for the
receiver part and all I/O signals, e.g. CLKM if enabled. The transmitter part and RF
frequency generation are not influenced.
7.7.6 Register Description
Register 0x03 (TRX_CTRL_0):
Table 7-27. Register 0x03 (TRX_CTRL_0)
Bit
7
6
5
4
Name
PAD_IO[1]
PAD_IO[0]
PAD_IO_CLKM[1]
PAD_IO_CLKM[0]
Read/Write
R/W
Reset Value
0
1
Bit
3
2
1
0
Name
CLKM_SHA_SEL
CLKM_CTRL[2]
CLKM_CTRL[1]
CLKM_CTRL[0]
Read/Write
R/W
Reset Value
1
0
1
The TRX_CTRL_0 register controls the drive current of the digital outputs and the
CLKM clock rate. It is recommended using the lowest value for the drive current to
reduce the current consumption and the emission of signal harmonics.
Bit 7:6 – PAD_IO
Refer to section 2.2.2.3.
Bit 5:4 – PAD_IO_CLKM
These register bits set the output driver strength of pin CLKM. It is recommended to
reduce the driver strength to 2 mA (PAD_IO_CLKM = 0) if possible. This reduces power
consumption and spurious emissions.
Table 7-28. CLKM Driver Strength
Register Bits
Value
Description
0
2 mA
1
4 mA
2
6 mA
PAD_IO_CLKM
3
8 mA
Bit 3 – CLKM_SHA_SEL
The register bit CLKM_SHA_SEL defines whether a new clock rate (defined by
CLKM_CTRL) is set immediately or gets effective after the next SLEEP cycle.
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