Debug in depth
C-14
Copyright 2000 ARM Limited. All rights reserved.
ARM DDI 0165B
The scan cells perform three basic functions:
capture
shift
update.
For input cells, the capture stage involves copying the value of the system input to the
core into the serial register. During shift, this value is output serially. The value applied
to the core from an input cell is either the system input or the contents of the parallel
register (loads from the shift register after UPDATE-DR state) under multiplexor
control.
For output cells, capture involves placing the value of a core output into the serial
register. During shift, this value is serially output as before. The value applied to the
system from an output cell is either the core output or the contents of the serial register.
All the control signals for the scan cells are generated internally by the TAP controller.
The action of the TAP controller is determined by current instruction and the state of the
TAP state machine.
Scan chain 1
Purpose
Scan chain 1 is used for communication between the debugger and
the ARM9E-S core. It is used to read and write data, and to scan
instructions into the instruction pipeline. The SCAN_N
instruction is used to select scan chain 1.
Length
67 bits.
Scan chain 1 provides serial access to RDATA[31:0] when the core is doing a read, and
to the WDATA[31:0] bus when the core is doing a write. It also provides serial access
to the INSTR[31:0] bus, and to the control bits, SYSPEED and WPTANDBKPT. For
compatibility with the ARM9TDMI, there is one additional unused bit that must be zero
when writing, and is UNPREDICTABLE when reading.
There are 67 bits in this scan chain, the order being (from serial data in to out):
1.
INSTR[31:0]
2.
SYSPEED
3.
WPTANDBKPT
4.
unused bit
5.
RDATA[31:0] or WDATA[31:0].
Bit 0 of RDATA or WDATA is therefore the first bit to be shifted out.