Programmer’s Model
ARM DDI 0165B
Copyright 2000 ARM Limited. All rights reserved.
2-9
2.7
Registers
The ARM9E-S has a total of 37 registers:
31 general-purpose 32-bit registers
6 32-bit status registers.
These registers are not all accessible at the same time. The processor state and operating
mode determine which registers are available to the programmer.
2.7.1
The ARM state register set
In ARM state, 16 general registers and one or two status registers are accessible at any
one time. In privileged modes, mode-specific banked registers become available.
The ARM state register set contains 16 directly-accessible registers, r0 to r15. A further
register, the Current Program Status Register (CPSR), contains condition code flags
and the current mode bits. Registers r0 to r13 are general-purpose registers used to hold
either data or address values. Registers r14, r15, and the CPSR have the following
special functions:
Link register
Register r14 is used as the subroutine Link Register (LR).
Register r14 receives a copy of r15 when a Branch with Link (BL
or BLX) instruction is executed.
You can treat r14 as a general-purpose register at all other times.
The corresponding banked registers r14_svc, r14_irq, r14_fiq,
r14_abt and r14_und are similarly used to hold the return values
of r15 when interrupts and exceptions arise, or when BL or BLX
instructions are executed within interrupt or exception routines.
Program counter
Register r15 holds the PC.
In ARM state, bits [1:0] of r15 are zero. Bits [31:2] contain the PC.
In Thumb state, bit [0] is zero. Bits [31:1] contain the PC.
In privileged modes, another register, the Saved Program Status Register (SPSR), is
accessible. This contains the condition code flags and the mode bits saved as a result of
the exception that caused entry to the current mode.