Programmer’s Model
2-16
Copyright 2000 ARM Limited. All rights reserved.
ARM DDI 0165B
2.8
The program status registers
The ARM9E-S contains a CPSR, and five SPSRs for exception handlers to use. The
program status registers:
hold information about the most recently performed ALU operation
control the enabling and disabling of interrupts
set the processor operating mode.
The arrangement of bits in the status registers is shown in
Figure 2-6.
Figure 2-6 Program status register
Note
The unused bits of the status registers might be used in future ARM architectures, and
must not be modified by software. The unused bits of the status registers are readable,
to allow the processor state to be preserved (for example, during process context
switches) and writable, to allow the processor state to be restored. To maintain
compatibility with future ARM processors, and as good practice, you are strongly
advised to use a read-modify-write strategy when changing the CPSR.
2.8.1
The condition code flags
The N, Z, C, and V bits are the condition code flags. They can be set by arithmetic and
logical operations, and also by MSR and LDM instructions. The ARM9E-S tests these
flags to determine whether to execute an instruction.
All instructions can execute conditionally on the state of the N, Z, C, and V bits in ARM
state. In Thumb state, only the Branch instruction can be executed conditionally. For
more information about conditional execution, refer to the ARM Architecture Reference
Manual.
28
29
30
31
M0
M1
M2
M3
M4
.
F
I
V
C
Z
N
Overflow
Condition code flags
T
.
Carry/Borrow/Extend
Zero
Negative/Less than
Mode bits
State bit
FIQ disable
IRQ disable
Reserved
26
27
9876543210
Control bits
Q
Sticky overflow