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| 型號(hào)： | MQ80C52TXXX-16SHXXX:RD |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁(yè)數(shù)： | 53/83頁(yè) |
| 文件大?。?/td> | 8336K |
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51
32117D–AVR-01/12
AT32UC3C
7.3
Block Diagram
Figure 7-1.
PM Block Diagram
7.4
I/O Lines Description
7.5
Product Dependencies
7.5.1
Interrupt
The PM interrupt line is connected to one of the interrupt controllers internal sources. Using the
PM interrupt requires the interrupt controller to be configured first.
7.5.2
Clock Implementation
In AT32UC3C, the HSB shares source clock with the CPU. Write attempts to the HSB Clock
Select register (HSBSEL) will be ignored, and it will always read the same as the CPU Clock
Select register (CPUSEL).
The PM bus interface clock (CLK_PM) is generated by the Power Manager. This clock is
enabled at reset, and can be disabled in the Power Manager. If disabled it can only be re-
enabled by a reset.
Table 7-1.
I/O Lines Description
Name
Description
Type
Active Level
RESET_N
Reset
Input
Low
Sleep Controller
Synchronous
Clock Generator
Reset Controller
Main Clock Sources
Sleep
Instruction
Power-on Reset
Detector(s)
Resets
Synchronous
clocks
CPU, HSB,
PBx
Interrupts
External Reset Pin
Reset Sources
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