參數(shù)資料
型號(hào): MQ80C52TXXX-30SBR
廠(chǎng)商: TEMIC SEMICONDUCTORS
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQFP44
文件頁(yè)數(shù): 102/141頁(yè)
文件大?。?/td> 7628K
代理商: MQ80C52TXXX-30SBR
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33
2486AA–AVR–02/2013
ATmega8(L)
Power
Management
and Sleep
Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
To enter any of the five sleep modes, the SE bit in MCUCR must be written to logic one and a
SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the MCUCR Register
select which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, or Standby)
will be activated by the SLEEP instruction. See Table 13 for a summary. If an enabled interrupt
occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four
cycles in addition to the start-up time, it executes the interrupt routine, and resumes execution
from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered
when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up
and executes from the Reset Vector.
Note that the Extended Standby mode present in many other AVR MCUs has been removed in
the ATmega8, as the TOSC and XTAL inputs share the same physical pins.
Figure 10 on page 25 presents the different clock systems in the ATmega8, and their distribu-
tion. The figure is helpful in selecting an appropriate sleep mode.
MCU Control Register
– MCUCR
The MCU Control Register contains control bits for power management.
Bit 7 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
purpose, it is recommended to set the Sleep Enable (SE) bit just before the execution of the
SLEEP instruction.
Bits 6..4 – SM2..0: Sleep Mode Select Bits 2, 1, and 0
These bits select between the five available sleep modes as shown in Table 13.
Note:
1. Standby mode is only available with external crystals or resonators
Bit
765
4321
0
SE
SM2
SM1
SM0
ISC11
ISC10
ISC01
ISC00
MCUCR
Read/Write
R/W
Initial Value
000
0000
0
Table 13. Sleep Mode Select
SM2
SM1
SM0
Sleep Mode
000
Idle
0
1
ADC Noise Reduction
010
Power-down
011
Power-save
100
Reserved
101
Reserved
110
Standby(1)
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