![](http://datasheet.mmic.net.cn/30000/MQ83C154DXXX-25-883R_datasheet_2377229/MQ83C154DXXX-25-883R_143.png)
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6384E–ATARM–05-Feb-10
AT91SAM9G20
the ECC Controller (ECC)
a chip select assignment feature that assigns an AHB address space to the external devices
a multiplex controller circuit that shares the pins between the different Memory Controllers
programmable CompactFlash support logic
programmable NAND Flash support logic
20.6.1
Bus Multiplexing
The EBI offers a complete set of control signals that share the 32-bit data lines, the address
lines of up to 26 bits and the control signals through a multiplex logic operating in function of the
memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and
output control lines at a stable state while no external access is being performed. Multiplexing is
also designed to respect the data float times defined in the Memory Controllers. Furthermore,
refresh cycles of the SDRAM are executed independently by the SDRAM Controller without
delaying the other external Memory Controller accesses.
20.6.2
Pull-up Control
The EBI_CSA Registers in the Chip Configuration User Interface permit enabling of on-chip pull-
up resistors on the data bus lines not multiplexed with the PIO Controller lines. The pull-up resis-
tors are enabled after reset. Setting the EBI_DBPUC bit disables the pull-up resistors on the D0
to D15 lines. Enabling the pull-up resistor on the D16-D31 lines can be performed by program-
ming the appropriate PIO controller.
20.6.3
Static Memory Controller
For information on the Static Memory Controller, refer to the section “Static Memory Controller”.
20.6.4
SDRAM Controller
For information on the SDRAM Controller, refer to the section “SDRAM Controller”.
20.6.5
ECC Controller
For information on the ECC Controller, refer to the section “ECC Controller”.
20.6.6
CompactFlash Support
The External Bus Interface integrates circuitry that interfaces to CompactFlash devices.
The CompactFlash logic is driven by the Static Memory Controller (SMC) on the NCS4 and/or
NCS5 address space. Programming the EBI_CS4A and/or EBI_CS5A bit of the EBI_CSA Reg-
ister in the Chip Configuration User Interface to the appropriate value enables this logic. For
details on this register, refer to the in the Bus Matrix Section. Access to an external Compact-
Flash device is then made by accessing the address space reserved to NCS4 and/or NCS5 (i.e.,
between 0x5000 0000 and 0x5FFF FFFF for NCS4 and between 0x6000 0000 and 0x6FFF
FFFF for NCS5).
All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are sup-
ported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are
not handled.