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參數(shù)資料
| 型號(hào)： | MR80C52EXXX-16SHXXX:R |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁(yè)數(shù)： | 46/143頁(yè) |
| 文件大?。?/td> | 4602K |
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14
XMEGA A3BU [DATASHEET]
8362F–AVR–02/2013
7.11
JTAG Disable
It is possible to disable the JTAG interface from the application software. This will prevent all external JTAG access to the
device until the next device reset or until JTAG is enabled again from the application software. As long as JTAG is
disabled, the I/O pins required for JTAG can be used as normal I/O pins.
7.12
I/O Memory Protection
Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the
I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is
enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers
themselves are protected by the configuration change protection mechanism.
7.13
Flash and EEPROM Page Size
The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the
flash and byte accessible for the EEPROM.
Table 7-2 on page 14 shows the Flash Program Memory organization and Program Counter (PC) size. Flash write and
erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash
access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the page
number and the least significant address bits (FWORD) give the word in the page.
Table 7-2.
Number of words and pages in the flash.
Table 7-3 on page 14 shows EEPROM memory organization. EEPROM write and erase operations can be performed
one page or one byte at a time, while reading the EEPROM is done one byte at a time. For EEPROM access the NVM
address register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give the page
number and the least significant address bits (E2BYTE) give the byte in the page.
Table 7-3.
Number of bytes and pages in the EEPROM.
Devices
PC size
Flash size
Page size
FWORD
FPAGE
Application
Boot
[bits]
[bytes]
[words]
Size
No of
pages
Size
No of
pages
ATxmega256A3B
U
18
256K + 8K
256
Z[8:1]
Z[18:9]
256K
512
8K
16
Devices
EEPROM
Page size
E2BYTE
E2PAGE
No of pages
size
[bytes]
ATxmega256A3BU
4K
32
ADDR[4:0]
ADDR[11:5]
128
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